A CMOS DCO design using delay programmable differential latches and a novel digital control scheme

Hasan, S. M. Rezaul

doi:10.1007/s00202-006-0037-z

Cited by 4 publications

(2 citation statements)

References 9 publications

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“…There are several ways to alter the frequency in a ring DCO. The frequency control can be implemented via current modulation, modification of the output capacitance of the inverters with switches and MOS varactance [12] or only MOS varactance [13]. The latter approach has been chosen in this project.…”

Section: Frequency Control Blocksmentioning

confidence: 99%

Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process

Bisiaux

Blokhina

Koskin

et al. 2020

2020 European Conference on Circuit Theory and Design (ECCTD)

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Section: Frequency Control Blocksmentioning

confidence: 99%

Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process

Bisiaux

Blokhina

Koskin

et al. 2020

2020 European Conference on Circuit Theory and Design (ECCTD)

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“…Different digitally controlled delay elements (DCDEs) have been reported in Refs. [10][11][12][13]. There are two parameters which modulate the output frequency of a ring oscillator.…”

Section: Introductionmentioning

confidence: 99%

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

2012

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Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits.Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A threetransistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591 W. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740 W. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998 W. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

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