This letter presents a fully integrated interface circuitry with a position-based charge qubit structure implemented in 22-nm FDSOI CMOS. The quantum structure is controlled by a tiny capacitive DAC (CDAC) that occupies 3.5×45 µm 2 and consumes 0.27 mW running at a 2-GHz system clock. The state of the quantum structure is measured by a single-electron detector that consumes 1 mW (including its output driver) with an area of 40×25 µm 2 . The low power and miniaturized layout of these circuits pave the way for integration in a large quantum core with thousands of qubits, which is a necessity for practical quantum computers. The CDAC output noise of 12 µV-rms is estimated through mathematical analysis while the ≤ 0.225 mV-rms input referred noise of the detector is verified by measurements at 3.4 K. The functionality of the system and performance of the CDAC are verified in a loopback mode with the detector sensing the CDAC-induced electron tunneling from the floating diffusion node into the quantum structure.

This brief presents a single-electron injection device for position-based charge qubit structures implemented in 22 nm FD-SOI CMOS. Quantum dots are implemented in local well areas separated by tunnel barriers controlled by gate terminals overlapping with a thin 5 nm undoped silicon film. Interface of the quantum structure with classical electronic circuitry is provided with single-electron transistors that feature doped wells on the classic side. A small 0.7×0.4 µm 2 elementary quantum core is co-located with control circuitry inside the quantum operation cell which is operating at 3.5 K and a 2 GHz clock frequency. With this apparatus, we demonstrate a single electron injection into a quantum dot.Index Terms-Single-electron injection device (SEID), cryogenic circuits, position-based charge qubit, quantum computer, quantum point contact (QPC), quantum operation cell, quantum dot (QD), fully depleted silicon-on-insulator (FD-SOI).

In this paper, we derive a mathematical model of an All-Digital Phase-Locked Loop (ADPLL) employing a timeto-digital phase detector. The model we suggest represents a nonlinear discrete-time map and provides significant benefits for the simulation of a single PLL, a network of PLLs or their design.In particular, the model allows us to take into account the jitter of the reference and local clocks and other noises. The mathematical model (the map) is then compared with a behavioural model implemented in MATLAB Simulink and displays identical results. The simulation of the mathematical and behavioural models are further compared with experimental measurements of a 65nm CMOS ADPLL and show a good agreement.

No abstract

No abstract