A CMOS Dual-<italic>RC</italic> Frequency Reference With ±200-ppm Inaccuracy From −45 °C to 85 °C

Abstract

This paper presents a 7-MHz CMOS RC frequency reference. It consists of a frequency-locked loop in which the output frequency of a digitally controlled oscillator (DCO) is locked to the combined phase shifts of two independent RC (Wien bridge) filters, each employing resistors with complementary temperature coefficients. The filters are driven by the DCO's output frequency and the resulting phase shifts are digitized by high-resolution phase-to-digital converters. Their outputs are then combined in the digital domain to realize a temperature-independent frequency error signal. This digitally assisted temperature compensation scheme achieves an inaccuracy of ±200 ppm from −45°C to 85°C after a two-point trim. The frequency reference draws 430 µA from a 1.8-V supply, while achieving a supply sensitivity of 0.18%/V and a 330-ppb Allan deviation floor in 3 s of measurement time. Index Terms-CMOS, digital frequency-locked loop (FLL), digitally controlled oscillator (DCO), integrated frequency reference, RC-based. , where he is currently pursuing the Ph.D. degree, with a focus on the design of energy-efficient CMOS temperature sensors. Fabio Sebastiano (S'09-M'10-SM'17) received the B.Sc. and M.Sc. degrees(cum laude) in electrical engineering from the University of Pisa, Pisa, Italy, in 2003 and 2005, respectively, the M.Sc. degree (cum laude) from the Sant'Anna School of Advanced Studies, Pisa, Italy, in 2006, and the Ph.D. degree from the

3.4 A 16MHz CMOS RC Frequency Reference with ±400ppm Inaccuracy from −45°C to 85°C After Digital Linear Temperature Compensation

“…Compared to LC (~20mW, ~100ppm) [1] or TD (~2mW, ~1000ppm) [2] references, RC references offer the lowest power consumption and competitive accuracy (< 1mW, 200ppm) [3]. However, due to the nonlinear temperature dependency of on-chip resistors, such references require complex temperature-compensation schemes based on higher-order correction polynomials and extensive calibration [3,4], or complicated analog compensation networks [5]. In this work, we present a 16MHz RC-based frequency reference that achieves ±400ppm inaccuracy from -45˚C to 85˚C after a digital 2-point trim.…”

Thermal synergies in 50 nanometer CMOS and below

“…A survey of the literature over the past 2 decades reveals a trend in the development of system‐on‐chip (SoC) integrated circuits geared towards the Internet of Things (IoT), wearable and wireless devices, and generally ‘smart’, less‐consuming, and more power‐efficient electronics. The need for accurate references constrained by low voltage (<1 V), current, and power allowances (<1 nW) has spurred a variety of calibration techniques to achieve BGR curvature correction [2,3] and poly and metal–shunt resistor trimming [4,5] by means of dynamic error correction methods [5], digitally assisted [6,7], programmable [8,9], or otherwise. A representative sample of the state‐of‐the‐art for such methods and diversity of applications thereof [2–13] can be found in Table (see Appendix ).…”

A 33-ppm/°C 240-nW 40-nm CMOS Wakeup Timer Based on a Bang-Bang Digital-Intensive Frequency-Locked-Loop for IoT Applications

“…Among fully integrated oscillators, conventional RC relaxation oscillators are limited in accuracy by the delay of powerhungry continuous-time comparators, which are vulnerable to PVT variations [4]- [6], [16]. To circumvent this problem, oscillators based on frequency-locked loops (FLL) have been employed, but they heavily rely on analog-intensive circuits, which require significant power, area and a high supply voltage [7]- [9], [14], [20]. Hence, they are not friendly to technology scaling in terms of area and required supply voltage.…”