A CMOS Low Pass Filter for SoC Lock-in-Based Measurement Devices

Abstract

This paper presents a fully integrated Gm–C low pass filter (LPF) based on a current steering Gm reduction-tuning technique, specifically designed to operate as the output stage of a SoC lock-in amplifier. To validate this proposal, a first-order and a second-order single-ended topology were integrated into a 1.8 V to 0.18 µm CMOS (Complementary Metal-Oxide-Semiconductor) process, showing experimentally a tuneable cutoff frequency that spanned five orders of magnitude, from tens of mHz to kHz, with a constant current consumption (below 3 µA/pole), compact size (<0.0140 mm2/pole), and a dynamic range better than 70 dB. Compared to state-of-the-art solutions, the proposed approach exhibited very competitive performances while simultaneously fully satisfying the demanding requirements of on-chip portable measurement systems in terms of highly efficient area and power. This is of special relevance, taking into account the current trend towards multichannel instruments to process sensor arrays, as the total area and power consumption will be proportional to the number of channels.

1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

“…Our proposal is based on a fixed g m input stage, with a continuously adjustable current steering (CS) technique in the output branch, which allows for G m -reduction and tunability. This technique has been previously presented in [30] applied to a 1.8 V mirrored Operational Transconductance Amplifier (OTA). This work presents and validates the experimental results of a modified 1.0 V-0.18 µm integrated LPF, also based on a mirrored OTA whose preliminary simulation results were presented in [31]; and a 1.0 V-0.18 µm specifically designed LPF using a folded-cascode core OTA to achieve an ultra-efficient power and area architecture.…”

“…A NMOS-input pair was used with a small gm1 in the order of ~µS and unity gain (k = 1) current mirrors to keep the gain, Gm, reduced. This scheme provides the same gain Gm = gm1 as a classic differential pair, but uncouples the input and output commonmode range at the cost of doubling the power consumption [30]. The folded cascode OTA is a single-stage high-gain structure, which requires a lower supply voltage than a typical cascode amplifier.…”

A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces

“…Examples of using the capacitance (Miller's) multiplication in front-ends can be found in [1,7]. However, the majority of the available literature focuses on LTA-based emulation of large resistances [2,3,[8][9][10][11][12][13][14][15][16][17][18]. LTAs emulate resistors as large as 10 7 -10 11 Ω while occupying a reasonable area of 0.01 mm 2 to 0.1 mm 2 [2,3,[8][9][10][11][12][13][14][15][16][17][18].…”

A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

“…The increasing appearance of long-life autonomous portable and wearable equipment [1][2][3][4][5][6][7][8] demanding miniaturized systems with decreasing power consumption has brought to the forefront the design of efficient power management units (PMU), where low dropout (LDO) regulators play a key role [9][10][11][12][13]. As shown in Figure 1, in battery-operated systems, the LDO generates, from the battery voltage V BAT , a stable, low-noise and accurate supply voltage V out under substantial changes of the battery voltage and the load current demanded to bias a specific system module, typically making use of multiple LDOs so as to optimize each module power consumption and, therefore, the global power efficiency.…”