A CMOS power amplifier with 180° hybrid on-chip coupler for 4G applications

Abstract

This paper presents a CMOS Class AB power amplifier with an on-chip 180 • hybrid coupler for 4G applications. Two-stage power amplifier architecture with a combination of low voltage core transistor and high voltage I/O transistors, is designed to achieve the power gain in the 180nm standard CMOS technology. The driver stage has a power gain of 18.5dB and linear output power of 12.9dBm. The power stage has a gain of 13.7dB and P 1dB of 24.4dBm. The paper also presents an onchip 180 • hybrid coupler, designed in the same technology, for combining the power generated from individual power amplifiers. The measured results of the coupler show an isolation better than -30dB, S11 better than -20dB and, S21 and S31 equal to -5.4dB, at 2.35GHz. The complete differential power amplifier using the on-chip coupler gives P 1dB of 26.4dBm and saturated output power of 27.4dBm. As compared to all the reported onchip couplers configurations, use of 180 • hybrid coupler leads to better load insensitivity as well as improved linearity due to the second harmonic cancellation.