A CMOS RISC CPU with on-chip parallel cache

8. Conclusion

“…The Assist cache [1] (Figure 2i) is a multi-lateral design where the B cache is used as a "staging area" for data entering the A (main) cache. On a hit, the data is returned to the processor the next cycle, but remains in the cache in which it is found.…”

“…Figure 2 shows representations of several multi-lateral cache configurations. Figure 2i shows the Assist cache configuration, used in the HP PA-7200 [1] [12]. All blocks that enter the cache from memory must enter through the Assist buffer (the B cache).…”

“…Cache [1], Victim Cache [2], and NTS Cache [3] have been shown to perform as well as or better than larger, single structure caches while requiring less die area [4] [5]. For a given die size, reducing the die requirements to attain a given rate of data supply can allow other resources to use the saved space --for example, more space dedicated to branch prediction, data forwarding, instruction supply, and increasing the size of the reorder buffer can serve to improve performance more than simply improving cache performance.…”

“…To address this, processor designers typically design for the largest possible caches that can still remain on the ever growing processor die. However, alternate, multi-lateral 1 cache designs such as the Assist Cache, Victim Cache, and NTS Cache have been shown to perform as well as or better than larger, single structure caches while requiring less die area. For a given die size, reducing the requirements to attain a given rate of data supply can allow more space dedicated for branch prediction, data forwarding, increasing the size of the reorder buffer, etc.…”

Retrospective: improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

“…One data-side application was a combined 2KB miss cache and stream buffer which was placed on the HP PA7100 microprocessor [3] while the primary caches remained off-chip. In this system they wanted large off-chip caches for good performance on large application programs.…”