A CMOS Variable Gain Amplifier with DC Offset Calibration Loop for Wireless Communications

Cheng, Zhih-Siou; Bor, Jenn-Chyou

doi:10.1109/vdat.2006.258115

Cited by 7 publications

(3 citation statements)

References 3 publications

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“…In direct conversion receivers, the presence of dc offset at the mixer outputs can cause significant signal distortion and saturation of subsequent gain stages. Calibration for static and/or dynamic dc offsets is presented in [13] and [14]. The techniques described before require no internal RF node probing, thus utilizing baseband or digitized signals.…”

Section: Prior Workmentioning

confidence: 99%

DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance Variability

Han

Kim

Chatterjee

2010

IEEE Trans. VLSI Syst.

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In the deep-submicrometer design regime, RF circuits are expected to be increasingly susceptible to process variations, and thereby suffer from significant loss of parametric yield. To address this problem, a postmanufacture self-tuning technique that aims to compensate for multiparameter variations is presented. The proposed method incorporates a "response feature" detector and "hardware tuning knobs," designed into the RF circuit. The RF device test response to a specially crafted diagnostic test stimulus is logged via the built-in detector and embedded analog-to-digital converter. Analysis and prediction of the optimal tuning knob control values for performance compensation is performed using software running on the baseband DSP processor. As a result, the RF circuit performance can be diagnosed and tuned with minimal assistance from external test equipment. Multiple RF performance parameters can be adjusted simultaneously under tuning knob control. The proposed concepts are illustrated for an RF lownoise amplifier (LNA) design and can be applied to other RF circuits as well. A simulation case study and hardware measurements on a fabricated 1.9-GHz LNAs show significant parametric yield enhancement (up to 58%) across the critical RF performance specifications of interest.

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Section: Prior Workmentioning

confidence: 99%

DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance Variability

Han

Kim

Chatterjee

2010

IEEE Trans. VLSI Syst.

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“…The modified scheme is to add another two signals to the input of integrator, which are the dc offset of the and paths taken from the polarity decision branches, or and , respectively. Thus, the integrator has three input signals (27) where the first term is the output from the multiplier, and the second and third terms are the dc offsets from the and paths, respectively. , , and are the scaling factors in the respective paths.…”

Section: I/q Mismatch Issuesmentioning

confidence: 99%

“…Also, a low corner frequency in the HPF may also lead to temporary loss of data [1]. Digital signal processing (DSP) is also an effective approach to compensate for dc offset, as reported in [9]- [11] and [27]. However, these approaches necessitate digital-to-analog conversion and consume a considerable amount of power.…”

Section: Introductionmentioning

confidence: 99%

A CMOS VGA With DC Offset Cancellation for Direct-Conversion Receivers

Zheng

Yan

2009

IEEE Trans. Circuits Syst. I

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A CMOS dB-linear variable gain amplifier (VGA) with a novel I/Q tuning loop for dc-offset cancellation is presented. The CMOS dB-linear VGA provides a variable gain of 60 dB while maintaining its 3-dB bandwidth greater than 2.5 MHz. A novel exponential circuit is proposed to obtain the dB-linear gain control characteristics. Nonideal effects on dB linearity are analyzed and the methods for improvement are suggested. A varying-bandwidth LPF is employed to achieve fast settling. The chip is fabricated in a 0.35-m CMOS technology and the measurement results demonstrate the good dB linearity of the proposed VGA and show that the tuning loop can effectively remove dc offset and suppress I/Q mismatch effects simultaneously.

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Noise Analysis and Optimization of Programmable Gain Amplifier with DC Offset Cancelation

Wang

et al. 2015

Circuits Syst Signal Process

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A CMOS Variable Gain Amplifier with DC Offset Calibration Loop for Wireless Communications

Cited by 7 publications

References 3 publications

DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance Variability

DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance Variability

A CMOS VGA With DC Offset Cancellation for Direct-Conversion Receivers

Noise Analysis and Optimization of Programmable Gain Amplifier with DC Offset Cancelation

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