A CNFET full adder cell design for high-speed arithmetic units

Ghanatghestani, Mokhtar Mohammadi; Ghavami, Behnam; Salehpour, Honeya

doi:10.3906/elk-1512-8

Cited by 8 publications

(6 citation statements)

References 10 publications

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“…Also, the new full adder based on CNFETs circuit improved the PDP, power consumption, and performance of the full adder cell [23]. Ghanaghestani et al [24] have suggested a full adder cell based on a parallel design using CNFETs. The suggested model affects the power consumption and speed, which results in reducing the critical path delay.…”

Section: Introductionmentioning

confidence: 99%

Taguchi Approach and Response Surface Analysis for Design of a High-performance Single-walled Carbon Nanotube Bundle Interconnects in a Full Adder

Ghorbani

Kashyzadeh

2020

IJE

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In this study, it was attempted to design a high-performance single-walled carbon nanotube (SWCNT) bundle interconnects in a full adder. For this purpose, the circuit performance was investigated using simulation in HSPICE software and considering the technology of 32-nm. Next, the effects of geometric parameters including the diameter of a nanotube, distance between nanotubes in a bundle, and width and length of the bundle were analyzed on the performance of SWCNT bundle interconnects in a full adder using Taguchi approach (TA). The results of Taguchi sensitivity analysis (TSA) showed that the bundle length is the most effective parameter on the circuit performance (about 51% on the power dissipation and 47% on the propagation delay). Moreover, the distance between nanotubes greatly affects the response compared to other parameters. Also, response surface method (RSM) indicated that an increase in the length of interconnects (L) improves the output of power dissipation. As the width of interconnects (W) and diameter of CNTs (D) increase the power dissipation also increases. Decrease in the distance between CNTs in a bundle (d) leads to an increase in power dissipation. The highest value of power dissipation is achieved if the maximum values for the parameters of length and width of interconnects (L, W), and diameter of CNTs (D) and the minimum value of the distance between CNTs in a bundle (d) are considered. It is also revealed that an increase in the length of interconnects (L) increases the propagation delay. Eventually, the optimum parameters are reported and the performance of the optimized system is compared using different methods (TA and RSM). Results indicate that the difference between the performance of optimal design of SWCNT bundle interconnects in a full adder predicted by different methods is less than 6% which is acceptable according to engineering standards.

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Section: Introductionmentioning

confidence: 99%

Taguchi Approach and Response Surface Analysis for Design of a High-performance Single-walled Carbon Nanotube Bundle Interconnects in a Full Adder

Ghorbani

Kashyzadeh

2020

IJE

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“…117 is controlled by varying the chirality vector based on the diameter the threshold voltage could be varied [2]. GNRs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage-related and alignment problems as faced by CNTFET devices [3].…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of different full adder cells using new technologies

Kumar

Somineni

Kumari

2020

IJRES

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<span>CMOS transistors are most widely used for the design of computerized circuits, when scaling down the nanometer technology these devices faces the short channel effects and causes I-V characteristics to depart from the traditional MOSFETs, So the researchers have developed the other transistors technologies like CNTFET and GNRFET. Carbon nanotube field effect transistor is one of the optimistic technologies and it is a three terminal transistor similar to MOSFET. The semiconducting channel between the two terminals called source and drain comprises of the nano tube which is made of carbon. Graphene nano ribbon filed effect transistor is the most optimistic technology here the semiconducting channel is made of graphene. When contrasted with barrel shaped CNTFETs, GNRFETs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage related and alignment problems as faced in CNTFET devices. This paper presents different 1-bit Full Adder Cells (FACs) like TG MUX-based FAC (TGM), MN MUX-based FAC (MNM), proposed TG Modified MUX-based FAC (TGMM) and another proposed MN Modified MUX-based FAC (MNMM) are designed using different technologies like CNTFET and GNRFET at 16nm technology with supply voltage of 0.85v and simulation is done by using Synopsys HSPICE Tool and the proposed designs are best when compared to the TGM and MNM FACs in terms of Static and Dynamic powers Dissipations and Delay.</span>

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“…They are especially interesting because their one-dimensional band structure suppresses backscattering and makes near-ballistic operation a possibility [4]. CNTs are interesting materials for nanoelectronic applications in terms of ballistic conduction for their long mean free path [5], which is of the order of a micrometer [6][7][8]. Because of these features, a considerable high-frequency performance for CNTFETs is expected.…”

Section: Introductionmentioning

confidence: 99%

“…Because of these features, a considerable high-frequency performance for CNTFETs is expected. Researchers have been studying and developing the CNTFET device behavior and its applications [8]. They divided the transistors based on carbon nanotubes into two groups: Schottky-Barrier CNTFETs (SB-CNTFETs) with metallic source/drain regions and MOS-like CNTFETs (MOS-CNTFETs) in which source and drain regions are heavily doped CNTs instead of the metallic parts [9][10][11].…”

Section: Introductionmentioning

confidence: 99%

“…To improve power consumption and save energy, the T-CNTFETs were proposed [14,24,25]. The subthreshold swing theoretical limit for MOS-CNTFETs is 60 mV/dec at room temperature, but T-CNTFETs have much better subthreshold swing than the MOS-like structure; therefore, these devices are proper candidates for applications with very low power consumption [2][3][4][5][6][7][8][9]26]. Despite desirable characteristics such as low power consumption, T-CNTFETs suffer from drawbacks such as small current ratio [9,24].…”

Section: Introductionmentioning

confidence: 99%

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An efficient structure for T-CNTFETs with intrinsic-n-doped impurity distribution pattern in drain region

Naderi¹,

Ghodrati²

2018

Turk J Elec Eng & Comp Sci

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In this paper, by using impurity distribution engineering of drain region, an efficient structure is proposed for tunneling carbon nanotube field-effect transistors (T-CNTFETs). The drain region of the proposed structure consists of two parts. The impurity density of the part close to the channel is intrinsic and the other is n-type with constant density of 1 nm −1 . In conventional T-CNTFETs, heavily doped drain causes a spiky drop of potential energy around the channel to drain junction resulting in a pathway for carriers in the valence band to tunnel to the conduction band which means ambipolar behavior and large leakage current. The proposed structure expands the longitudinal distance between the bands at this junction and reduces the band-to-band tunneling (BTBT) and improves leakage current and ambipolar behavior. Moreover, current ratio, delay time, power delay product, cut-off frequency, and subthreshold swing as important characteristics are enhanced so that the proposed structure can be more attractive for circuit designers. Also, design considerations for intrinsic region length were done and mentioned. To simulate the devices, self-consistent solution of Schrodinger and Poisson equations and nonequilibrium Green's Function method were employed.

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A CNFET full adder cell design for high-speed arithmetic units

Cited by 8 publications

References 10 publications

Taguchi Approach and Response Surface Analysis for Design of a High-performance Single-walled Carbon Nanotube Bundle Interconnects in a Full Adder

Taguchi Approach and Response Surface Analysis for Design of a High-performance Single-walled Carbon Nanotube Bundle Interconnects in a Full Adder

Design and analysis of different full adder cells using new technologies

An efficient structure for T-CNTFETs with intrinsic-n-doped impurity distribution pattern in drain region

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