Carbon Nanotube field-effect transistor (CNFET) can be a good alternative to the MOS transistors for high performance Static Random Access Memory (SRAM). The SRAM use as the cache for computers and many portable devices. Carbon nanotube field effect transistors are employed to realize the new design methodology. Main features of this technology provide multi-Vt circuitry with the flexibility which is highly important to MVL design. Ternary logic has fundamentally the potential of high computational speed in comparison with conventional binary logic. This paper presents a novel design of a ternary memory cell based on CNFETs. The proposed design is simulated by HSPICE on CNFET model with 0.9 V power supply. Simulation results illustration the improvement in terms of standby power consumption and speed in comparison with previous designs.

Carbon nanotube field-effect transistors (CNFETs) utilize an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure, which holds great promise for the future of integrated circuits. In this paper, a full adder cell based on a parallel design using CNFETs is presented. The main objective of designing this full adder cell is to reduce critical path delay in CNFET-based adder circuits. The proposed design positively affects speed and power consumption by shortening the data path. In order to evaluate the proposed design, several simulations were performed with different load capacitors, frequencies, and temperatures using HSPICE in 32-nm CMOS and 32-nm CNFET technologies. The proposed full adder cells were compared with five other full adder cells using 4-bit ripple carry adder (RCA) and 8-bit RCA circuits with power consumption, speed, and power delay product parameters. The obtained results indicate that the proposed design is faster than other designs due to a shortened data path. The results of the simulations confirm the higher efficiency of the proposed full adder cell with respect to other designs.

A novel approximate Full Adder cell is presented which is based on the ‎combination of standard CMOS logic and pass transistor logic styles. The ‎carbon nanotube field-effect transistor technology is used to simulate and implement ‎the proposed cell. Comprehensive simulations at various power supplies, output loads, and ‎ambient temperatures are conducted using the HSPICE tool. According to simulation results, its ‎delay, power-delay product, energy-delay product, and normalized energy-delay-‎area product improve by 18%, 10%, 39%, and 15% compared with the best existing ‎design. The effects of diameter variations of carbon nanotubes on the functionality of ‎the circuits are studied by Monte Carlo transient analysis. Simulation results confirm that ‎the proposed cell is resistant to the process variations. At the application level, all circuits are ‎employed in image blending to assess their efficacy in terms of peak signal-to-noise ratio ‎and structural similarity index criteria using the MATLAB tool. Simulation ‎results of image processing indicate that the proposed cell has a reasonable functionality and ‎produces output images with adequate quality to be inferred by humans.‎

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