A code decompression architecture for VLIW processors

Abstract

In embedded system design, memory has been one of the most restricted resources. Reducing program size has been an important goal when designing an embedded system. Most of the previous work on code compression has targeted RISC architectures. Recently VLIW processors became very populal; particularly for signal processing. Decompression speed is especially important for VLIW architectures given that the length of the instruction word is long. Furthermore, modern VLJW architectures use flexible instruction formats, which require new code compression approaches. Previous work has assumed that instruction positions within the long instruction word correspond to spec$cfinctional units. In contrast, our code compression algorithm is capable of compressing flexible instruction formats, where any functional unit can be used for any position in the instruction word. We demonstrate our methods by applying it to the TMS32OC6x architecture. We also compare two techniques for decompressing the VLJW instruction packet to reduce the decompression time. A fast parallel decompression architecture is described, which is implemented in TSMC 0.25 technology.

Practical Data Compression for Modern Memory Hierarchies

“…Compression was successfully applied not only to the application data, but also to the code itself [122,137,42,140,41,136,139,13,252,60,247]. The primary goal in these works was usually to reduce the program footprint (especially in the context of embedded devices).The reduced footprint can allow for more instructions to be stored in the instruction caches, and hence reduce the number of instruction cache misses, which, in turn, improves performance.…”

Compiler optimization and ordering effects on VLIW code compression

“…The code compression techniques applied to date on multipleissue processors (particularly the more original rigid VLIW processors, but also recently targeting variable execution set architectures) are limited to the works of Nam et al [21], Ishiura and Yamaguchi [10], Prakash et al [20], Xie et al [23][24][25] and Larin and Conte [11]. This is only a subset of the techniques available for both data compression and single-issue code compression.…”

“…Xie et al [23,25] are the first works to really target a VLES (various length execution set) such as the TMS320C6x where bit0 of each instruction tells the architecture whether the next instruction may be executed with the current set of instructions or not. Xie uses a reduced-precision arithmetic coding technique combined with a Markov model (statistical method) and applies it to similar systems with different sized sub-blocks.…”

“…The compression ratios in our study take into account the compression The performance and run-time overhead of this sort of decompression scheme has been investigated in other papers [7,14,15,17,22,25] and is beyond the scope of this paper. Although code compression generally results in reduced performance as a result of the hardware required, some studies have shown that applying code compression to post-cache architectures produces a benefit to performance through reduced cache-misses and fewer instruction fetches [19].…”

Pbiw

“…Diante disso, vários trabalhos com foco em redução do tamanho de instruções utilizaram conceitos e técnicas da área de compressão de código, sendo uma parte destes estudos voltados para as arquiteturas VLIW [27,31,34,48,49,50], que é o foco deste trabalho de mestrado.…”