A Codec Architecture for the Compression of Short Data Blocks

Abstract

This work proposes a lossless data compression algorithm for short data blocks. The proposed compression scheme combines a modified move-to-front algorithm with Huffman coding. This algorithm is applicable in storage systems where the data compression is performed on block level with short block sizes, in particular, in non-volatile memories. For block sizes in the range of 1[Formula: see text]kB, it provides a compression gain comparable to the Lempel–Ziv–Welch algorithm. Moreover, encoder and decoder architectures are proposed that have low memory requirements and provide fast data encoding and decoding.

Pipelined decoder for the limited context order Burrows–Wheeler transformation

“…The required hardware resources (number of look-up tables (LUT), number of registers, and RAM size in bits) are presented in Table 7. We compare the proposed decoder with implementations of PDLZW [32] and MTF-Huffman decoding [33]. The proposed BWT decoder requires about twice the logic and memory elements compared with the MTF + Huffman approach.…”

“…In this section, we present synthesis results for the proposed limited context BWT decoding architecture for the Xilinx Virtex 7 FPGA. The proposed decoder is compared with a decoder for the parallel‐dictionary‐Lempel‐Ziv‐Welch (PDLZW) algorithm [32] with four dictionaries and the decoder for a combined coding scheme consisting of the MTF algorithm and Huffman coding [33].…”

“…For the proposed decoder the total SP‐ and DP‐RAM size (in bits) can be estimated as The required hardware resources (number of look‐up tables (LUT), number of registers, and RAM size in bits) are presented in Table 7. We compare the proposed decoder with implementations of PDLZW [32] and MTF–Huffman decoding [33]. The proposed BWT decoder requires about twice the logic and memory elements compared with the MTF + Huffman approach.…”

Efficient VLSI architecture for the parallel dictionary LZW data compression algorithm

“…Universal data compression for flash memory systems has recently gained interest [1][2][3][4][5][6][7][8][9] because data compression can improve the storage capacity and the flash memory lifetime. Compression of redundant data reduces the amount of data transferred from the host to the flash system.…”

“…Data compression for such applications requires high data throughput that can only be achieved using hardware implementations. Moreover, it requires a universal data compression algorithm that can be used with small data blocks [6, 8].…”