A codesign synthesis from an MPEG-4 decoder dataflow description

Abstract

ISBN: 978-1-4244-5309-2 - WOSInternational audienceThe elaboration of new and innovative systems such as MPSoC (Multiprocessor System on Chip) which are made up of multiple processors, memories and IPs lies on the designers to achieve a complex codesign work. Specific tools and methods are needed to cope with the increasing complexity of both algorithms and platforms. Our approach to design such systems is based on the usage of a high level of abstraction language called RVC CAL. This language is dataflow oriented and thus points out the concurrency and parallelism of algorithms. Moreover CAL is supported by the OpenDF simulator and by two code generators called CAL2C (software generator) and CAL2HDL (hardware generator). The MPEG expert group has recently elaborated the Reconfigurable Video Coding (RVC) standard which defines the RVC CAL language as reference for MPEG video decoder descriptions. This paper introduces the opportunities to design an innovative system involving hardware and software IPs, embedded processors and memories from a CAL model. Practical results on a FPGA are provided with a codesign solution of an MPEG4 Simple Profile (SP)

A unified hardware/software co-synthesis solution for signal processing systems

“…The first tool that permitted the CAL to HDL was the OpenDF framework (a CAL simulator) with the use of OpenForge as a backend for the Verilog HDL generation. Often in RVC-CAL literature this tool is called as CAL2HDL [9,12]. XLIM OpenDF code generation does not support all the RVC-CAL subset and it is too slow compared to the XLIM generation of the Orcc.…”

Design of a processor optimized for syntax parsing in video decoders

“…updating the core of the processor by adding the hardware code required to process a specific instruction, 2. updating the ISA and the software compiler (e.g. GCC), 3. adding the specific instruction to the debugger (e.g.…”

“…We implemented the parser on an embedded processor and updated its ISA to evaluate the performance. The MPEG-4 video parser provided by RVC is still limited on embedded processors because it has not been optimized for software processing [3]. Thus, we replaced it with a hand-coded parser which has been developed according to the MPEG-4 standard.…”

“…the showbits instruction is decoded, 2. if necessary the registers used by the showbits instruction are initialized, 3. the location and the size of the N bits to extract from the M-bits word are read from the register, 4.…”

“…In a previous paper, we presented a method and results to implement a video decoder on a codesign architecture made up of a general purpose soft-core and FPGA. Performance was restricted by the hardware soft-core generalist architecture and the software syntax parser which was not optimized to be processed on a soft-core [3]. This paper presents our work on the codesign architecture, especially on the processor architecture so as to improve performance while keeping flexibility.…”