A Codesigned Integrated Photonic Electronic Neuron

Abstract

In the modern era of artificial intelligence, increasingly sophisticated artificial neural networks (ANNs) are implemented, which pose challenges in terms of execution speed and power consumption. To tackle this problem, recent research on reduced-precision ANNs opened the possibility to exploit analog hardware for neuromorphic acceleration. In this scenario, photonic-electronic engines are emerging as a short-medium term solution to exploit the high speed and inherent parallelism of optics for linear computations needed in ANN, while resorting to electronic circuitry for signal conditioning and memory storage. In this paper we introduce a precision-scalable integrated photonic-electronic multiply-accumulate neuron, namely PEMAN. The proposed device relies on (i) an analog photonic engine to perform reduced-precision multiplications at high speed and low power, and (ii) an electronic front-end for accumulation and application of the nonlinear activation function by means of a nonlinear encoding in the analog-to-digital converter (ADC). The device, based on the iSiPP50G SOI process for the photonic engine and a commercial 28 nm CMOS process for the electronic front end, has been numerically validated through cosimulations to perform multiply-accumulate operations (MAC). PEMAN exhibits a multiplication accuracy of 6.1 ENOB up to 10 GMAC/s, while it can perform computations up to 56 GMAC/s with a reduced accuracy down to 2.1 ENOB. The device can trade off speed with resolution and power consumption, it outperforms its analog electronics counterparts both in terms of speed and power consumption, and brings substantial improvements also compared to a leading GPU.

Analysis of Integration Technologies for High-Speed Analog Neuromorphic Photonics

“…Lower propagation losses have been reported exploiting specific process steps, with a notable 0.4 dB/cm [47]. Additionally, SOAs make this platform able to recover losses and, in neuromorphic chips, to implement diagonal matrices with gain [16]. Moreover, the non-linear behavior of SOAs can be exploited to both recover power and apply an activation function in all-optical neural networks, as demonstrated in [48].…”

“…However, the shot noise doubles as well, due to the contribution of both detectors. The total SFDR becomes [16]:…”

“…As this technology is still at an early stage of development, improvements are expected in terms of SFDR, bandwidth, ER, and V π [36]. This does not hold for the modulator length, which is likely to prevent the implementation of very complex all-optical neuromorphic circuits in this platform [16].…”

“…Among all analog approaches, photonics-based ones have the potential to meet the power consumption, bandwidth, and latency requirements for DNN deployment, being a versatile technology able to develop a notable variety of neural architectures comprising convolutional DNN, spiking neural networks, and reservoir computing [13], [14]. Leveraging the growing maturity of integration platforms, photonic integrated circuits (PICs) are widely used for analog information processing [15] with a growing number of PICs proposed for neuromorphic computing [16].…”