A column-parallel clock skew self-calibration circuit for time-resolved CMOS image sensors

Miao, Lianghua; Yasutomi, Keita; Imanishi, Shoichiro; Kawahito, Shoji

doi:10.1587/elex.12.20150911

Cited by 5 publications

(9 citation statements)

References 10 publications

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“…This challenge is mainly noticed with the variable-resistor array delay element (Zhang and Kaneko 2015 ; Maymandi-Nejad and Sachdev 2005 ). Nonetheless, this drawback may not be applied provided that proper design techniques are utilized, as in the case with the digitally-controlled SCI delay element implemented by (Miao et al 2015 ) which has shown to produce fine and linear delay steps within a relatively wide delay range. The digitally-controlled delay elements have the upper hand when good process portability, short design time, simple and robust design, and good power management are considered together in the design.…”

Section: Digitally-controlled Delay Elementsmentioning

confidence: 99%

“…Programmable delay lines with sub-gate delay resolution have been realized using many circuit topologies and techniques. They mainly involve: changing the capacitive loading (SCI) mechanism reported in (Schidl et al 2012 ; Abas et al 2007a ; Pao-Lung et al 2005 ; Miao et al 2015 ) and some of the current-starving delay-controlling techniques reported in (Maymandi-Nejad and Sachdev 2005 ; Saint-Laurent and Swaminathan 2001 ; El Mourabit et al 2012 ) which are mentioned earlier in the third and fourth sections of this paper, delay difference between two delay paths (sometimes called VDL) (Xanthopoulos 2009 ; Guang-Kaai et al 2000 ; Nuyts et al 2014 ), employing phase interpolation technique through, for example, utilizing DLLs as delay lines (Xanthopoulos 2009 ; Yang 2003 ), utilizing a capacitor charging along with comparators controlled by a DAC (Suchenek 2009 ; Klepacki et al 2015 ), and utilizing an analog differential buffer (Nuyts et al 2014 ).…”

Section: Open Research Issues and Conclusionmentioning

confidence: 99%

“…For example, a coarse counter is cascaded with interpolators based on digital delay lines (Kalisz 2004 ). Another solution is to employ both analog and DCDLs together in one single design to make use of the unique advantages of both of these differently controlled CMOS delay line types (Markovic et al 2013 ; Miao et al 2015 ). Utilizing phase interpolators with DCDLs is another solution without the need for cascading multiple DCDLs (Xanthopoulos 2009 ).…”

Section: Open Research Issues and Conclusionmentioning

confidence: 99%

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A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

et al. 2016

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A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

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Section: Digitally-controlled Delay Elementsmentioning

confidence: 99%

Section: Open Research Issues and Conclusionmentioning

confidence: 99%

Section: Open Research Issues and Conclusionmentioning

confidence: 99%

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A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

et al. 2016

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“…Similar problems arise in time resolved CMOS image sensors and timeinterleaved ADC, the influence of clock skew on the accuracy of time resolution is very important. To solve this problem, column parallel skew calibration circuits have been proposed and demonstrated its effectiveness [26,27,28]. A statistics-based background calibration and digital calibration scheme for timing skew is employed in timeinterleaved flash ADC [29,30].…”

Section: Introductionmentioning

confidence: 99%

A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

Guo

2020

IEICE Electron. Express

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A synchronous driving approach for stitching CMOS image sensor is proposed. Dual terminal signal line driver structure must be considered in the design of row control for high definition CMOS image sensor pixel array. However, as the size of the array increases further, the traditional synchronization technologies such as clock tree cannot be applied because of the stitching technology. Furthermore, this invalidity will cause DC shoot through and dead line. Based on the adaptive delay phase-locked loop, dual terminal signal line driver with highly efficient synchronization for pixel array is realized in a single die CMOS image sensor with 225M pixels and large area of 120 × 120 mm 2. The comparison results show that the timing matching improves by two orders of magnitude, and the consistency reaches 99.95%.

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“…This modeling aims to clarify the current issues of range resolution toward further improved range resolution. For short calibration times, background skew calibration is implemented using a column-parallel digital delay-locked loop (DLL) and a dual clock tree structure [34]. In this paper, the skew calibration is applied to the three-tap lock-in pixel.…”

Section: Introductionmentioning

confidence: 99%

A Sub-100 $\mu$ m-Range-Resolution Time-of-Flight Range Image Sensor With Three-Tap Lock-In Pixels, Non-Overlapping Gate Clock, and Reference Plane Sampling

Yasutomi

Yushi

Kagawa

et al. 2019

IEEE J. Solid-State Circuits

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This paper aims to propose a time-of-flight (TOF) range imager with high range resolution in the sub-100 µm range. The range imager employs a TOF measurement technique that uses an impulse photocurrent response and a three-tap lock-in pixel based on the lateral electric field modulation. To reduce the clock skew of the gating clocks, a column-parallel digital delaylocked loop (DLL) with a dual clock tree is implemented with a short calibration time of approximately 42 µs. A non-overlapping gate clock generation included in the skew calibration circuit effectively suppresses the photogenerated-charge partitioning for reduced nonlinearity for distance measurements. Reference plane sampling (RPS) is proposed to reduce low-frequency jitter that limits the range resolution in the light-pulse trigger. In this technique, a reference pixel array is embedded in the same focal plane of the main pixel array to sample and cancel the correlated jitter in the light trigger. The prototype range imager with 192 × 4 effective pixels is implemented in a 0.11-µm CMOS image sensor technology. Using the RPS, a range resolution of 64 µm rms has been achieved, corresponding to a 430-fs time resolution with a 25-mm range. The range resolution has a large column-to-column deviation due to the jitter induced by the column-parallel gating buffers. In noisy columns, jitter that acts as random telegraph noise (RTN) is observed. Index Terms-CMOS image sensor (CIS), delay-locked loop (DLL)-based skew calibration, high range resolution, lateral electric field modulator (LEFM), lock-in pixel, non-overlapping gate clock, photogenerated-charge partitioning, range imaging, reference plane sampling (RPS), skew calibration, time-offlight (TOF).

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A column-parallel clock skew self-calibration circuit for time-resolved CMOS image sensors

Cited by 5 publications

References 10 publications

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

A Sub-100 $\mu$ m-Range-Resolution Time-of-Flight Range Image Sensor With Three-Tap Lock-In Pixels, Non-Overlapping Gate Clock, and Reference Plane Sampling

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