A Commercial 65 nm CMOS Technology for Space Applications: Heavy Ion, Proton and Gamma Test Results and Modeling

Roché, Philippe; Gasiot, Gilles; Uznanski, Slawosz; Daveau, Jean-Marc; Torras-Flaquer, Josep; Clerc, Sylvain; Harboe-Sørensen, R.

doi:10.1109/tns.2010.2041790

Cited by 38 publications

(19 citation statements)

References 19 publications

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“…While experience of hard errors due to radiation in short-tomedium term GEO missions is not expected [10], testing of the earlier correlator, implemented in the same CMOS technology, predicts about one soft error per day in GEO [11]. Any soft error occurring in the readout logic is likely to invalidate an entire data set as opposed to single value changes for errors in any other part of the chip.…”

Section: Data Readoutmentioning

confidence: 99%

A 3-GHz reconfigurable 2/3-level 96/48-channel cross-correlator for synthetic aperture radiometry

Ryman

Emrich

Svensson

et al. 2017

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference

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Abstract-We present a cross-correlator ASIC for synthetic aperture imaging of Earth's atmosphere. Reconfigurability as a 2-level 96-channel or 3-level 48-channel cross-correlator provides adaptability to a wider array of applications. Implemented in a 65-nm CMOS process, the cross-correlator is capable of running at clock speeds of up to 3 GHz. In 2-level 96-channel mode, the cross-correlator consumes only 1.1 W at 2.5 GHz and 1.2 V, yielding a power efficiency of 96 µW/prod/GHz. The 450-Mb/s readout speed and double-buffering reduce blanking time of the interferometer system to a minimum.

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Section: Data Readoutmentioning

confidence: 99%

A 3-GHz reconfigurable 2/3-level 96/48-channel cross-correlator for synthetic aperture radiometry

Ryman

Emrich

Svensson

et al. 2017

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference

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“…Based on the proposed approach, the predicted cross sections are plotted in Figure 6. The experimental heavy ion upset cross sections in [26,27] are also plotted in the same diagram for comparison.…”

Section: Nm Srammentioning

confidence: 99%

“…The estimated cross sections from two models (improved model and previous one in [14]) and experimental heavy ion upset cross sections in [26,27] are plotted in Figure 6 (bottom). Besides, the data at low-LET region are zoomed in for comparison in the same figure (top).…”

Section: Nm Srammentioning

confidence: 99%

“…The SRAM memory cell is of standard 6T architecture with a bit cell area of 0.525 μm 2 . The predicted cross-section results based on the approach in this paper and the experimental data obtained from [3,27] for 65 nm technology process is shown in Figure 7. Besides, the Monte Carlo radiative energy deposition (MRED) prediction results from [3] are plotted in the same figure for comparison.…”

Section: Nm Srammentioning

confidence: 99%

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Prediction of low-LET ion induced single event upset cross sections for advanced SRAM

Zhou

2013

Journal of Nuclear Science and Technology

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This paper describes a simple circuit-level simulation-based approach to predict single event upset cross section induced by low-linear energy transfer (LET) ions for advanced bulk static random access memory (SRAM). A basic Simulation Program with Integrated Circuit Emphasis (SPICE) model with effective collection depth considered is developed for performing single event analysis quickly and efficiently. Through this circuit-level simulation model, radiation effects can be shown as the SPICE-simulated curve of LETs versus the corresponding affected distances, which are used for upset cross-section prediction. Furthermore, a fine-grain geometric model for cross-section prediction with fine sensitivity coefficient considered is utilized in the prediction. The calculated results based on this method are in good agreement with experimentally measured results reported for six-transistor SRAM fabricated in 90 nm and 65 nm process technologies.

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“…The layout uses both standard-and high-V T devices; the latter to reduce standby power. Neither the architecture nor the process is radiation hardened, but with technology scaling comes an intrinsical hardening [5]. While the design will fail in the case of a hard error, a single-event upset (SEU) will not cause any major problem.…”

Section: Architecturementioning

confidence: 99%

3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry

Ryman

Emrich

Andersson

et al. 2011

2011 IEEE Custom Integrated Circuits Conference (CICC)

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Abstract-A high-speed low-power cross-correlator ASIC has been implemented in a 65-nm CMOS process for the purpose of synthetic aperture radiometry from geostationary orbiting earth observation satellites. The chip performs cross-correlation on all individual signal pairs from 64 digital 1-bit inputs, which amounts to 2016 individual cross-correlation products. The experimental evaluation, using a specially developed PCB, demonstrates that the 3-mm 2 chip has a top performance of 3.6 GHz at a 1.2 V supply, at which it dissipates 790 mW.

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A Commercial 65 nm CMOS Technology for Space Applications: Heavy Ion, Proton and Gamma Test Results and Modeling

Cited by 38 publications

References 19 publications

A 3-GHz reconfigurable 2/3-level 96/48-channel cross-correlator for synthetic aperture radiometry

A 3-GHz reconfigurable 2/3-level 96/48-channel cross-correlator for synthetic aperture radiometry

Prediction of low-LET ion induced single event upset cross sections for advanced SRAM

3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry

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