A Communication-Aware Topological Mapping Technique for NoCs

Tornero, Rafael; Orduña, Juan M.; Palesi, Maurizio; Duato, J.

doi:10.1007/978-3-540-85451-7_98

Cited by 23 publications

(15 citation statements)

References 8 publications

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“…In order to achieve this goal, we propose a new topological mapping technique that can be applied to application-specific NoCs with both regular and irregular topologies [6]. Since this technique has been designed for NoCs based on distributed routing [7], [8], the second step consists of adapting this technique to support NoC platforms using source routing [9].…”

Section: The Proposed Approach and Methodologymentioning

confidence: 99%

Improving topological mapping on NoCs

Tornero

Orduña

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

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Section: The Proposed Approach and Methodologymentioning

confidence: 99%

Improving topological mapping on NoCs

Tornero

Orduña

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

Self Cite

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“…This table provides a measurement of the proportional cost for communicating each possible pair of network nodes, according to the topology and the routing algorithm used. The correlation of this model with real network performance has been experimentally shown, even for situations where the network is under deep saturation [11]. The table of communication costs contains the equivalent distances for all the origindestination node pairs.…”

Section: (B) (A)mentioning

confidence: 99%

“…A different approach takes into account the network resources and the communication pattern generated by the tasks assigned to different cores [11]. The method is based on modeling the network as a table of distances (or costs) between each pair of source/destination nodes, taking into account the network topology and the routing function (the term node denotes the router implemented in each core, connected directly the IP assigned to that core and also to other routers in the network through network links).…”

Section: Communication-aware Task Mapping Techniquementioning

confidence: 99%

“…On the other hand, a communication-aware task mapping technique that is based on a technique originally proposed for off-chip irregular networks [10] has been recently adapted to NoCs [11]. This technique globally matches the communication requirements of the application(s) tasks running on the different IPs with the existing network resources.…”

Section: Introductionmentioning

confidence: 99%

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A Communication-Driven Routing Technique for Application-Specific NoCs

Tornero

Orduña

Mejı́a

et al. 2010

Int J Parallel Prog

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Networks on Chip (NoCs) have been shown as an efficient solution to the complex on-chip communication problems derived from the increasing number of processor cores. One of the key issues in the design of NoCs is the reduction of both area and power dissipation. As a result, two-dimensional meshes have become the preferred topology, since it offers low and constant link delay. Unfortunately, manufacturing defects or even real-time failures often make the resulting topology to become irregular, preventing the use of traditional routing algorithms. This scenario shows the need for topology-agnostic routing algorithms that provide a valid routing solution when applied over any topology. This paper proposes a new communication-driven routing technique that optimizes the network performance for Application-Specific NoCs. This technique combines a flexible, topology-agnostic routing algorithm with a communication-aware mapping technique that matches the traffic generated by the application with the available network bandwidth. Since the mapping technique can be pruned as needed in order to fit either quality function values or time constraints, this technique can be adapted to fit with different computational costs. The evaluation results show that it significantly improves network performance in terms of both latency and power consumption.

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“…Orduna et al [18], [22], [23], [24], [25] explore communication-aware task mapping strategies that account for the communication requirements of parallel tasks and bandwidth in different parts of the network. They model the network resources as a table of costs for each pair of communicating processors.…”

Section: Related Workmentioning

confidence: 99%

Power-aware MPI task aggregation prediction for high-end computing systems

Liu

Nikolopoulos

Cameron

et al. 2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing (IPDPS)

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Abstract-Emerging large-scale systems have many nodes with several processors per node and multiple cores per processor. These systems require effective task distribution between cores, processors and nodes to achieve high levels of performance and utilization. Current scheduling strategies distribute tasks between cores according to a count of available cores, but ignore the execution time and energy implications of task aggregation (i.e., grouping multiple tasks within the same node or the same multicore processor). Task aggregation can save significant energy while sustaining or even improving performance. However, choosing an effective task aggregation becomes more difficult as the core count and the options available for task placement increase. We present a framework to predict the performance effect of task aggregation in both computation and communication phases and its impact in terms of execution time and energy of MPI programs. Our results for the NPB 3.2 MPI benchmark suite show that our framework provides accurate predictions leading to substantial energy saving through aggregation (64.87% on average and up to 70.03%) with tolerable performance loss (under 5%).

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A Communication-Aware Topological Mapping Technique for NoCs

Cited by 23 publications

References 8 publications

Improving topological mapping on NoCs

Improving topological mapping on NoCs

A Communication-Driven Routing Technique for Application-Specific NoCs

Power-aware MPI task aggregation prediction for high-end computing systems

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