A Compact 0.2–0.3-V Inverse-Class-F₂₃ Oscillator for Low 1/f ³ Noise Over Wide Tuning Range

Abstract

We introduce a new mode of oscillation in an LCtank: an inverse class-F 23 . In contrast to the conventional class-F oscillators, in which a high value of the real impedance (i.e., resistance) is presented to the third (in class-F 3 ) or/and to the second (in class-F 2 /class-F 23 ) oscillator harmonics via an auxiliary resonance, here low resistive impedances (resembling a non-ideal short) are presented at both the second and third harmonics. This is made possible by tight magnetic coupling in the differential and common modes, respectively, afforded by a new compact 2:3 transformer. Being largely free from the harmonics in the voltage waveform and their possible deleterious phase shift effects on the flicker noise up-conversion, the phase noise performance in the flicker and thermal regions is further improved by narrowing the conduction angle. The 2:3 step-up transformer also provides a high passive gain to help with the startup in face of low supply. The switched-capacitor banks and cross-coupled transistor pair are carefully integrated under the transformer with a special arrangement of native (high-resistivity) substrate layer to mitigate their effect on the oscillation while reducing the area by 30%. The proposed digitally controlled oscillator (DCO) is implemented in 28-nm CMOS and achieves −95 dBc/Hz and −118 dBc/Hz at 100 kHz and 1 MHz offsets, respectively, while operating at a 0.3 V supply. The measured 1/ f 3 corner stays within 60 to 100 kHz over the 35% tuning range (TR) (from 2.02 to 2.87 GHz). This results in a figure-of-merit (FoM) with normalized TR (FoM T ) of −196 and −199 dB at 100 kHz and 1 MHz offsets, respectively, is a record in the space of ≤0.5 V and ≤1 mW.

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

“…The size of the transformer is optimized for the intended operating frequency to achieve high Q-factor but without excessive coupling to the substrate, whose self-resonant frequency (where k GD vanishes) is around 5× the operating frequency. The dummy filling with the native layer ("NT_N" layer for high substrate resistivity [76] and extended in all the directions by 30 μm away from the coils) is reused from the inductor's process design kit (PDK) for easily passing the design rule check and minimizing the Q-factor loss.…”

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial

“…edges with an ADC [6], [46], [52]- [54] appears a promising solution, while its fractional-N operation may rely on a digitalto-time converter (DTC) [9], [10], [55]- [57] or DAC [5], [46], [53], [58]. Considering such a conceptual ADC-based TDC 'sampling' the oscillator's slope, its TDC gain, t tdc (unit: s/bit), is derived as…”

A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications

“…In the last few years, several flicker PN reduction techniques have been proposed at RT: 1) inserting resistances in series to the drain of oscillation sustaining devices [33]; 2) narrowing down the conduction angle of oscillation sustaining devices [34], [35]; 3) shifting the phase of the gate voltage against the drain voltage by tuning the capacitance ratio of the gate and drain capacitors in a transformer-based complementary oscillator [36]. Nevertheless, adding drain resistors degrades an oscillator's PN in the 20 dB/decade region with low supply and high current consumption.…”