A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios

Abstract

This paper describes a compact and low-power frequency synthesizer with quadrature phase output for software-defined radios (SDRs). The proposed synthesizer is constructed using a core phase-locked loop (PLL), which is coupled with a fractional-N injection-locked frequency divider (ILFD). The fractional-N injection-locking operation is achieved by the proposed self-synchronized gating injection technique. The principle of a fractional-N injection locking operation and the concept of the proposed circuits are described in detail. Analysis for predicting the locking range of the proposed fractional-N ILFD is investigated. A digital calibration scheme is adopted in order to compensate for process, voltage, and temperature (PVT) variations. Implemented in a 65 nm CMOS process, this work demonstrates continuous frequency coverage from 10 MHz to 6.6 GHz with quadrature phase output while occupying a small area of 0.38 mm 2 and consuming 16 to 26 mW, depending on the output frequency. The normalized phase noise achieves -135.3 dBc/Hz at an offset of 3 MHz and -95.1 dBc/Hz at an offset of 10 kHz, both from a carrier frequency of 1.7 GHz.

Digitally Assisted Analog and RF Circuits

“…The center of lock range becomes close to a free-running frequency of injection-locked oscillator, so it can be easily calibrated by using a frequency counter [21], [22]. In addition, a fractional division ratio can be realized by an injection-locked frequency divider using the gated-injection technique [23], which is used with a lock-range calibration [24], [25]. A frequency multiplication is also important function of the injection-locked oscillators, and injection-locked PLLs using this multiplication capability have been reported and achieve very low jitter and lower power comsumption [26], [27].…”

MDLL/PLL dual-path clock generator

“…Moreover, recent publications [3][4] show that synchronization between internal running and external injection edges can be handled within reasonable accuracy. Nonetheless, both the conventional injection-locking or phase realignment techniques are realized by adapting injecting or phase-realigning functionality into a conventional CP-PLL, and the drawbacks of a conventional PLL still remain in the prior work.…”

0.1–5 GHz wideband ΔΣ fractional‐N frequency synthesiser for software‐defined radio application

“…The LCPLL has superior phase noise performance with relatively narrow tuning range. To design the wideband LCPLL, several researches were presented recently [4][5][6][7][8][9][10]. The WBFSs with quadrature mixer were presented in Ref.…”

“…[4][5][6][7], but the mismatch of the mixer caused large spur level. The WBFS with self-synchronised gating injection-locked frequency divider (ILFD) was also presented to extend the covered frequency range [8]. However, it is not a robust choice because the central frequency of the ILFD varies with process, voltage and temperature (PVT) variation, and thus leads to undesirable phase noise and spur level deterioration.…”