MDLL/PLL dual-path clock generator

Abstract

This paper proposes an MDLL/PLL dual-path clock generator. By splitting a single delay line into two halves, both a voltage controlled delay-line (VCDL) and a voltage controlled oscillator (VCO) can be implemented. Since both the integral and proportional paths can be configured in this way, stabilizing zero is inherently obtained. Elimination of the zeroinsertion resistor in a loop-filter mitigates several drawbacks of a conventional charge-pump (CP) PLL. The comparison between the conventional CP-PLL and the proposed architecture reveals significant power and chip area savings with better jitter performance.