A compact FPGA-based architecture for elliptic curve cryptography over prime fields

Abstract

Abstract-This paper proposes an FPGA-based applicationspecific elliptic curve processor over a prime field. This research targets applications for which compactness is more important than speed. To obtain a small datapath, the FPGA's dedicated multipliers and carry-chain logic are used and no parallellism is introduced. A small control unit is obtained by following a microcode approach, in which the instructions are stored in the FPGA's Block RAM. The use of algorithms that prevent Simple Power Analysis (SPA) attacks creates an extra cost in latency. Nevertheless, the created processor is flexible in the sense that it can handle all finite field operations over 256-bit prime fields and all elliptic curves of a specified form. The comparison with other implementations on the same generation of FPGAs learns that our design occupies the smallest area.

Completing the Complete ECC Formulae with Countermeasures

“…In this work, we concentrate on a low-resource implementation. Some publications that also use the same approach are by Roy et al [16], Pöpper et al [17] and Vliegen et al [18], where the last one is the basis of this work. All of these implementations use the same approach of having a very small datapath on which the algorithmic operations are executed in a sequential way.…”

“…To compensate this loss in time, resource-constrained architectures are usually carefully optimized to try to do all operations in the least amount of cycles. For example, Roy et al [16] optimize the reduction for NIST curves, while Vliegen et al [18] optimize for Montgomery multiplication.…”

“…The hardware architecture is a standalone 32-bit elliptic curve processor as presented in [18]. A block diagram of this processor is depicted in Figure 1 and consists of the typical components: an instruction memory, a data memory, a modular arithmetic and logic unit (ALU) and a control unit.…”

Implementing Complete Formulas on Weierstrass Curves in Hardware

“…Table 5 contains different implementations of elliptic-curve scalar multiplications, but they have different optimization goals. For example we top [39] in terms of milliseconds per scalar multiplication when compared with the same FPGA and field arithmetic. On the other hand [34,26] have a trade-off between area and time, even though their proposal was aimed and optimized for a different FPGA than ours.…”

“…The approach was to parallelize Montgomery multiplication and formulas for point addition and doubling on the curve. Vliegen et al [39] attempted to reduce the resources with a small core aimed at 256-bit primes.…”