A compact, low power AES core on 180nm CMOS process

Dao, Van-Lan; Hoang, Van‐Phuc; Nguyen, Anh-Thai; Le, Quy-Minh

doi:10.1109/icicdt.2016.7542040

Cited by 11 publications

(4 citation statements)

References 14 publications

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“…Table 6 provides the AES implementation at 180 nm CMOS technology. Here, the implementations of Dao et al (2016), Kuo and Verbauwhede (2001); Verbauwhede et al (2003), Kim et al (2003); Li (2006), Cao and Li (2009); Alma’Aitah and Abid (2010); Lee et al (2016), Van Lan et al (2018); and Cast (2019) are selected for the comparison. The table contains some blank cells (–) that represent the data being unavailable.…”

Section: Experimental Results For Fpga and Asic Implementationsmentioning

confidence: 99%

“…Software implementations of the AES and PRESENT ciphers for low-cost smartphones have been compared in Andrés et al (2016) . Some of the popular complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) implementations of the AES cipher on 180 nm technology include Dao et al (2016), Kuo and Verbauwhede (2001); Verbauwhede et al (2003), Kim et al (2003); Li (2006), Cao and Li (2009); Alma’Aitah and Abid (2010); Lee et al (2016), Van Lan et al (2018); and Cast (2019). AES as a coprocessor for embedded cryptographic and biometric applications has been designed and fabricated using TSMC 6 M 180 nm CMOS technology by Tiri et al (2005).…”

Section: Introductionmentioning

confidence: 99%

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Design, integration and implementation of crypto cores in an SoC environment

Pandey

Gupta

Karmakar

2022

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Purpose The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations. Design/methodology/approach An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided. Findings FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed. Originality/value The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

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Section: Experimental Results For Fpga and Asic Implementationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design, integration and implementation of crypto cores in an SoC environment

Pandey

Gupta

Karmakar

2022

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“…One of the searchable symmetric encryption (SSE) used in IoT devices was proposed by DAO et al [15] who presented a compact and low energy consumption AES core, using a small S-box and an improved key in an expansion block. The authors presented two optimizations: the first was the optimization of the S-box; the second was the optimization of the Rcon block.…”

Section: Literature Reviewmentioning

confidence: 99%

Intrusion Detection System for AES Encripted Low-Power IoT Networks

Luiz

Copetti

Bertini

et al. 2021

Anais Do XII Computer on the Beach - COTB '21

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The introduction of the IPv6 protocol solved the problem of providingaddresses to network devices. With the emergence of the Internetof Things (IoT), there was also the need to develop a protocolthat would assist in connecting low-power devices. The 6LoWPANprotocols were created for this purpose. However, such protocolsinherited the vulnerabilities and threats related to Denial of Service(DoS) attacks from the IPv4 and IPv6 protocols. In this paper, weprepare a network environment for low-power IoT devices usingCOOJA simulator and Contiki operating system to analyze theenergy consumption of devices. Besides, we propose an IntrusionDetection System (IDS) associated with the AES symmetric encryptionalgorithm for the detection of reflection DoS attacks. Thesymmetric encryption has proven to be an appropriate methoddue to low implementation overhead, not incurring in large powerconsumption, and keeping a high level of system security. The maincontributions of this paper are: (i) implementation of a reflectionattack algorithm for IoT devices; (ii) implementation of an intrusiondetection system using AES encryption; (iii) comparison ofthe power consumption in three distinct scenarios: normal messageexchange, the occurrence of a reflection attack, and runningIDS algorithm. Finally, the results presented show that the IDSwith symmetric cryptography meets the security requirements andrespects the energy limits of low-power sensors.

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“…, c 6 , for strong one-wayness and pairwise independence (Section 2.2). There are several AES-128 implementations designed for RFID applications and optimized for low resource requirements [16,17], and the cost of implementing right circular shifts and xor's is almost negligible.…”

Section: Proposed Protocolmentioning

confidence: 99%

5G-Compliant Authentication Protocol for RFID

2020

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The term “Internet of Things” was originally coined when radio frequency identification (RFID) technology was being developed to refer to applications where RFID tagged objects and sensors enabled computers to achieve effective situational awareness without human intervention. Currently, this term encompasses a myriad of medium/small devices connected to the Internet. On the other hand, 5G is a key enabling technology that will support next generation wireless communications. Moreover, 5G aims to realize the “Internet of Everything”. Surprisingly, despite the expected relationship between these two technologies, RFID tags have not been properly integrated into 4G and it is not clear if this will change in 5G. RFID is considered as a parallel technology where, at best, it has connection to the core network using back-end servers as gateways between the two technologies. With the aim of overcoming this problem, this paper proposes a 5G compliant RFID protocol that allows RFID tags to act as fully fledged 5G subscribers while taking into account the main characteristics of RFID systems. This proposal leverages the separation between USIM and mobile equipment within the user equipment to implement a 5G compliant protocol where tags accomplish the authentication part, as 5G subscribers, while readers assume the mobile equipment role, carrying out the 5G communication and most of the resource consuming tasks.

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A compact, low power AES core on 180nm CMOS process

Cited by 11 publications

References 14 publications

Design, integration and implementation of crypto cores in an SoC environment

Design, integration and implementation of crypto cores in an SoC environment

Intrusion Detection System for AES Encripted Low-Power IoT Networks

5G-Compliant Authentication Protocol for RFID

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