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To enhance the utilization efficiency of Internet of Things (IoT) and cyber-physical system technologies, more collaboration in data transmission is recommended. These applications receive data from multiple sensors; hence, addition of efficient data acquisition system becomes mandatory. Past research works report use of data sharing among the tasks; however, this is only possible as long as the data meets the time-sensitive requirements of the tasks. To have an efficient communication between the different nodes of the IoT applications, this research work proposes use of reconfigurable first-in, first-out (r-FIFO) design to acquire data. This would not only reduce total sensing time but also the energy consumption, which is a conspicuous concernment in IoT systems for the offline scenarios. This paper first provides an optimal algorithm for FIFO tasks in the offline case, and later the r-FIFO architecture is synthesized on the FPGA board using ZYBO (zynq-7000). Further, the design is being implemented in SCL 180 nm CMOS ASIC technology. Performance measurement is performed by evaluating the frequency, total power, and the energy per bit of the design.

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Purpose The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations. Design/methodology/approach An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided. Findings FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed. Originality/value The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.