A Unified Architecture for AES/PRESENT Ciphers and its Usage in an SoC Environment

Pandey, Jai Gopal; Gupta, Sanskriti; Karmakar, Arindam

doi:10.1109/lascas45839.2020.9069025

Cited by 4 publications

(1 citation statement)

References 7 publications

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“…A report on performance metrics for a set of lightweight block ciphers is given by Kerckhof et al (2012) The design is implemented in four metal layer SCL 180 nm CMOS technology semi-conductor laboratory (SCL), (which is a TowerJazz enabled foundry), consumes 69,092 GE and 1.85 mm 2 chip area Pandey et al (2018b). Recently, an integrated design for the AES and PRESENT cipher realization in an SoC environment is presented by Pandey et al (2020). In the design, 0.87 mm 2 chip area is used with a 2 Â 2 die size.…”

Section: Introductionmentioning

confidence: 99%

Design, integration and implementation of crypto cores in an SoC environment

Pandey

Gupta

Karmakar

2022

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Purpose The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations. Design/methodology/approach An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided. Findings FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed. Originality/value The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

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Section: Introductionmentioning

confidence: 99%

Design, integration and implementation of crypto cores in an SoC environment

Pandey

Gupta

Karmakar

2022

Self Cite

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Adaptive Counter Clock Gated S-Box Transformation Based AES Algorithm of Low Power Consumption and Dissipation in VLSI System Design

Subramanian¹,

Venkatachalam²,

Saroja³

2021

J. Phys.: Conf. Ser.

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Advanced Encryption Standard (AES) is an effective algorithm trending today. According to the key length, it works efficiently. Here three types of key lengths are used such as 128, 192, and 256 bits. This paper introduced an Adaptive Counter-Clock (ACC) S-Box algorithm. This algorithm rectifies the error during data encryption and secure data from hackers. In this paper, we have done power consumption, power dissipation, and reduced the area size. Field Programmable Gate Array (FPGA) is utilized for hardware execution in the encryption process. Inverse Mix Column, Inverse Sub Bytes (S-Box) and Inverse Shift Row stages takes place in the decryption, so that the receiver can read the message in plain text which was sent by the sender. For this the receiver should have the same key used by the sender for encryption process. RTL coding is done using Verilog HDL, Xilinx ISE 14.7 FPGA will be used in the implementation.

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