Adaptive Counter Clock Gated S-Box Transformation Based AES Algorithm of Low Power Consumption and Dissipation in VLSI System Design

Subramanian, K. G.; Venkatachalam, M.; Saroja, M.

doi:10.1088/1742-6596/1979/1/012066

Cited by 6 publications

(6 citation statements)

References 12 publications

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“…Another work 32 compared the scalability, memory, power, and area consumption between AES and eXtendedTEA (XTEA). The research work in Reference 33 proposed an Adaptive Counter clock (ACC) technique in the AES S‐box algorithm. With this technique, the authors rectified error in the AES iteration process and four stages of S‐box combinational logic was deployed.…”

Section: Literature Reviewmentioning

confidence: 99%

Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array‐A survey

Renugadevi

Thangallapally²,

Vemula³

et al. 2022

Security and Privacy

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With the majority of users migrating to a cloud computing platform, the responsibility for data security has increased considerably. As data with various levels of sensitivity moves out of the confines of the system firewall, there is no control over where it resides; it depends on the cloud server being used. This makes the use of secured cryptographic algorithms necessary to improve data security and maintain the confidentiality of data. The encryption algorithm used most extensively today is the Advanced Encryption Standard (AES). Hardware acceleration with Field Programmable Gate Array can improve the performance of AES. This study examines various approaches for improving data encryption methods that can be utilized as hardware accelerators to improve the fundamental AES cipher. Some research publications suggest ways to boost throughput while others advise ways to save area and power. Many subsequent developments have also used other cryptographic methods such as RSA and ECC to improve key management security. This study examines the outcomes of multiple ways for metrics including throughput, area, power, and data security, and explains some of the best implementation solutions for each metric individually.

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Section: Literature Reviewmentioning

confidence: 99%

Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array‐A survey

Renugadevi

Thangallapally²,

Vemula³

et al. 2022

Security and Privacy

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“…In a conventional architecture, each step or process of subkey generation must be delayed until the previous Similarly, multiple keys are generated from the designed FJMKE architecture, and it is used to accomplish the encryption over multiple plain texts. For example, the generation of W15 using the FJMKE architecture is expressed in the following Equation (8).…”

Section: Fjmke Architecturementioning

confidence: 99%

“…The methods of encryption/decryption are classified into two types such as symmetric and asymmetric methods. In that, symmetric cryptography uses only one key for encryption and decryption, whereas asymmetric cryptography uses two distinct keys to accomplish the encryption and decryption [7][8][9]. Symmetric cryptography is extensively used among all cryptographic methods due to its low energy necessities and simplicity.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

Kumar

Balmuri²,

Marchewka

et al. 2021

Sensors

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Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture’s key expansion section to increase the speed of producing subkeys. The fork–join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.

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“…Besides being competent, unnoticeable, and robust, the least significant bit (LSB) steganography is among the most reliable methods for image steganography. It has been widely employed to conceal text behind images in various fields, including encryption, anti-hacking, and secure online data sharing [11], [12]. In the initial phase of this investigation, a video file was read and converted into frames.…”

Section: Introductionmentioning

confidence: 99%

Hide Text within a Video Using Data Encryption Standard (DES) Technology

Al-Agaili,

Hamdan Ali,

Naser

2024

SAR Journal

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It is possible to encode a message using one of the encryption algorithms and embed the text within a selected frame from the video, as this is considered a more secure method for handling confidential information. The concealment is deemed unbreakable because the message is encrypted in a manner that prevents decryption, making it challenging to retrieve the hidden text. In this study, Data Encryption Standard (DES) technology was employed to embed the last bits of the chosen video frame using a software-based approach. The frames, decoders, PSNR, and encrypted messages are illustrated in various videos. The results demonstrated minimal impact on the video's accuracy, as concealment occurs in the least significant bits (LSB), preserving the overall precision of the video.

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Adaptive Counter Clock Gated S-Box Transformation Based AES Algorithm of Low Power Consumption and Dissipation in VLSI System Design

Cited by 6 publications

References 12 publications

Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array‐A survey

Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array‐A survey

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

Hide Text within a Video Using Data Encryption Standard (DES) Technology

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