A Compact Rail-to-Rail Class-AB CMOS Buffer With Slew-Rate Enhancement

Abstract

Two prior-art transconductance amplifier-based rail-to-rail class-AB analog buffers are examined. Their analysis reveals that the output current drive capability for large input voltages is restricted. To mitigate this drawback, a relatively simple slew-rate enhancement scheme is proposed. The new scheme allows the buffer's speed to be increased by over 200% with only a very small increase in static power consumption (1.25%) and silicon area (3%). The proposed and the two conventional buffers were fabricated in a 0.35-μm CMOS technology for a power supply of 3 V. Measurements verify the superior slew-rate performance of the new buffer for rail-to-rail step responses.

A low power adaptive bias fully differential operational amplifier

“…The input voltage is always low so a Rail-to-Rail [11-12] input stage has been used which help to power efficient operation. The output stage is a c1ass-AB [13] which is used for various purposes like for high gain, reducing the distortion loss at the output and transfer power to load without loss. So the Op-Amp circuit can be divided into three parts.…”

“…The advantages of class AB output stages are, it provides very less nonlinear distortion, and it consumes very low power and provide a very good current capability to drive the capacitive load [13]. In summary the reason of using c1ass-AB stage is it provide good linearity, consume less power and a very good current drive capability when loaded with capacitor.…”

A Rail-To-Rail Hign Speed Class-AB CMOS Buffer with Low Power and Enhanced Slew Rate

“…To achieve the rail-to-rail swing, an NMOS pair and an PMOS pair added in parallel configuration [11].The CMR voltage range of the n-channel pair is written as;…”

Class-AB CMOS Buffer with Low Power and Low Leakage Using Transistor Gating Technique

“…Class-AB amplifiers are mainly used for low power consumption and to gain reduced cross-over distortion. Chutham Sawigun et al, proposed paper "A compact rail-to-rail class-AB CMOS buffer with slew rate enhancement" in 2012 [9]. Two prior-art transconductance are used by this class-AB analogue buffer, where DFVF transconductors (Differential flipped voltage follower) is used as basic circuit cell in the buffer design.…”

“…The proposed paper is based on the [9] which is proposed with new current leakage scheme. Buffer circuits are mostly used to run the large capacitive load at high speed.…”