A class-AB four-quadrant current multiplier constituted by a class-AB current amplifier and a current splitter which can handle input signals in excess of ten times the bias current is presented. The proposed circuit operation is based on the exponential characteristic of BJTs or subthreshold MOSFETs. The multiplier is designed using the latter devices and achieves very low power consumption. Simulation results show that from a 0.65 V supply, the proposed circuit consumes 12.4 nW static power while less than 230 dB total harmonic distortion is achieved for an input modulation index up to 10.Introduction: Based on the well-known exponential characteristics of BJTs or weak inversion MOSFETs, four-quadrant current multiplier circuits have been designed from different principles, e.g. transconductor/ conveyor based [1] and translinear circuit based [2] current multipliers. Most of them are restricted to class-A operation that does not allow the input signals' swing to become higher than their bias currents.In this Letter, a fully class-AB four-quadrant analogue current multiplier is presented. The proposed multiplier is formed by a dual output current amplifier which is biased by controlled currents generated from a current splitter. Both the amplifier and splitter circuits can be realised from the same basic circuit block, called Sinh transconductor, which provides class-AB operation. Therefore, fully class-AB multiplication is obtained. Owing to the class-AB operation, the multiplier circuit can be designed to process high input signal amplitudes while its bias current can be kept low. Circuit simulation using a 0.13 mm model parameter shows that, for a 0.5 nA bias current, input currents with amplitudes of 5 nA can be applied to the circuit and good fourquadrant multiplication is performed.

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Two prior-art transconductance amplifier-based rail-to-rail class-AB analog buffers are examined. Their analysis reveals that the output current drive capability for large input voltages is restricted. To mitigate this drawback, a relatively simple slew-rate enhancement scheme is proposed. The new scheme allows the buffer's speed to be increased by over 200% with only a very small increase in static power consumption (1.25%) and silicon area (3%). The proposed and the two conventional buffers were fabricated in a 0.35-μm CMOS technology for a power supply of 3 V. Measurements verify the superior slew-rate performance of the new buffer for rail-to-rail step responses.

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Abstract-According to recent physiological experiments, the envelope and phase of speech signals are required to enhance the perceptive capability of a cochlear implant processor. In this paper, the design of an analog complex gammatone filter is introduced in order to extract both envelope and phase information of the incoming speech signals as well as to emulate the basilar membrane spectral selectivity. The gammatone impulse response is first transformed into the frequency domain and the resulting 8 th -order transfer function is subsequently mapped onto a state-space description of an orthonormal ladder filter. Using this approach, the real and imaginary transfer functions that share the same denominator can be extracted using two different C matrices. This results in a compact filter structure. The proposed filter is designed using G m -C integrators and sub-threshold CMOS devices in AMIS 0.35μm technology. Simulation results using Cadence RF Spectre confirm the design principle and ultra low power operation.