A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS

Combined effect of loop delay and reference clock jitter in first-order digital bang-bang phase-locked loops

“…2 [5], [9]. Since a BPD (1-bit TDC) can be implemented as a sampling register in which the divided clock samples the reference clock [3], it is sufficient to consider only the time instants of the rising clock edges, denoted by tr and t d , respectively. The bit stream from the BPD, whose binary quantization operation is modeled by the signum function sgn, is fed into the DLF which, for our first-order loop, consists of a proportional path with gain KP .…”

“…The resulting class of bang-bang PLLs (BBPLLs) is widely used in clock and data recovery circuits due to its highspeed capabilities [2]. Recently, a digital BBPLL (DBBPLL) has been demonstrated to be suitable for high-bandwidth synthesis [3], and will be the focus of our study. Typical in a DPLL implementation is (excess) loop delay due to the latency of the digital building blocks and, in particular, the arithmetic operations performed by the DLF (pipelining).…”

Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

“…While they are usually implemented based on the charge-pump architecture [2]- [4], the continuing trend to replace analog functions by digital blocks has resulted in digital BBPLL (DBBPLL) implementations suitable for high-bandwidth frequency synthesis [5]- [9]. A block diagram of a second-order DBBPLL is shown in Fig.…”

“…1 [10]. The binary output of the BPD is directly fed into the digital loop filter (DLF), whose output tunes the frequency of a digitally controlled oscillator (DCO)-the only analog block [5]. Advantages of this digital approach include compact circuit realization and easy programmability of loop dynamics.…”

“…Assumption A1 is typically made in a practical loop design, where it is common to choose ≫ [2]- [4]. Moreover, since the LF is implemented in the digital domain, the gain coefficients and are integer powers of two [5], [6], [8]. Assumption A2 corresponds to nonaccumulative jitter, because consecutive random timing errors do not influence each other; the Gaussian distribution accounts for the random timing errors being caused by thermal electronic noise [11].…”