Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

Tertinek, Stefan; Feely, Orla

doi:10.1109/tcsii.2011.2149650

Cited by 5 publications

(4 citation statements)

References 23 publications

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“…Also, in Musa and Carusone (2007) modeling and designing BBCDR with first order loop was presented. In Tertinek and Feely (2011), the effect of non-accumulative reference clock jitter (referred to as the input jitter throughout) on the output jitter in second-order BBPLL was modeled as a 2-D Markov chain. In Cheng et al (2007), the steady-state analysis of BBCDR was performed for the cases with no jitter in the input and the value of output jitter amplitude was derived.…”

Section: Introductionmentioning

confidence: 99%

“…Many efforts have been made to analyze the nonlinear loop dynamic of BBCDR (Cheng et al, 2007;Chun and Kennedy, 2008;Da Dalt, 2006;Lee et al, 2004;Li et al, 2008;Musa and Carusone, 2007;Tertinek and Feely, 2011;Tertinek et al, 2010;Walker, 2003). However, almost none of these references have provided an analysis for designing the CDR directly so a more general analysis should be implemented.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A novel approach to analysis and design of bang-bang CDR circuits

Adrang

Naimi²

2013

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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Purpose -Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized. The paper aims to discuss these issues. Design/methodology/approach -The presented method is general enough to be used for designing the BBCDR loop parameters to meet SONET jitter transfer requirements (loop bandwidth and jitter peaking). Findings -In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized by formulating the time domain waveforms. As a result, a new equation is presented to obtain angular frequency. Also, the jitter tolerance is expressed in closed form as a function of loop parameters. The validity of the resulted equations is verified through HSPICE simulations using TSMC 0.18-mm CMOS process. Simulation results show that good conformance between analytical equations and simulation results. Originality/value -The proposed approach offers two advantages compared to conventional designing methods. First, this approach does not consider any value restriction to the capacitor. Second, a new condition has been presented to guarantee that the value of jitter peaking is approximately zero. The presented method is general enough to be used for designing the BBCDR.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A novel approach to analysis and design of bang-bang CDR circuits

Adrang

Naimi²

2013

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

View full text Add to dashboard Cite

show abstract

“…Many efforts have been made to analyze the nonlinear loop dynamic of BBCDR (Da Dalt, 2006;Chun and Kennedy, 2008;Tertinek et al, 2010b;Musa and Carusone, 2007;Tertinek and Feely, 2011;Cheng et al, 2007;Walker, 2003;Lee et al, 2004;Li et al, 2008). The effect of jitter can be accurately analyzed using Markov models, but their applicability has been limited to first-order loop (without loop filter capacitor) (Da Dalt, 2006;Chun and Kennedy, 2008;Tertinek et al, 2010b).…”

Section: Introductionmentioning

confidence: 99%

“…Also, in Musa and Carusone (2007) modeling and design of BBCDR with first-order loop has been presented. In Tertinek and Feely (2011), the effect of non-accumulative reference clock jitter (referred to as the input jitter throughout) on the output jitter in second-order BBPLLs has been modeled as a 2-D Markov chain.…”

Section: Introductionmentioning

confidence: 99%

Modeling of jitter in bang‐bang clock and data recovery circuits

Adrang

2013

COMPEL - The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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Purpose -Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized. Design/methodology/approach -The presented method is enough to be used for designing the BBCDR loop parameters. Findings -In this paper, jitter characteristics of the BBCDR are characterized. As a result, a new equation is presented to obtain angular frequency. Also, the jitter tolerance is expressed in closed form as a function of loop parameters. The analysis is verified using behavioral simulations in MATLAB. Simulation results show that good conformance between analytical equations and simulation results. Originality/value -The proposed approach offers two advantages compared to conventional designing methods. First, this approach does not consider any value restriction to the capacitor. Second, a new condition has been presented to guarantee that the value of jitter peaking is approximately zero.

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Jitter and metastability analysis and modeling of multilevel bang‐bang phase detector

Salem

Saneei

Abbasi‐Moghadam

2020

Circuit Theory & Apps

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SummaryBang‐bang phase detector (BBPD) is one of the essential blocks in the phase‐locked loop and clock and data recovery that are used in transceivers. But BBPD has the metastability problem as data change in timing window. It suffers from not only metastability failure but also quantization noise, which causes output jitter. In this paper, the novel model is presented to evaluate the effect of both metastability and jitter on ML‐BBPD, and also, it is shown that multilevel BBPD (ML‐BBPD) has the improved quantization noise in comparison with the Alexander BBPD. In this model, it is shown that by increasing the oversampling ratio, the quantization noise is decreased, and with the metastability effect and the increment of quantization steps, the characteristic curve of the ML‐BBPD becomes more smoothed. Also, the output jitter of ML‐BBPD, in which metastability failure is diminished, is modeled. The error function in the model is simulated at system level and compares with the results achieved from simulation at circuit level to prove the validity of the proposed model. The simulation is done in TSMC 65‐nm CMOS technology under 1‐V supply voltage to compare the characteristic of ML‐BBPD for various number of sampling clocks.

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Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

Cited by 5 publications

References 23 publications

A novel approach to analysis and design of bang-bang CDR circuits

A novel approach to analysis and design of bang-bang CDR circuits

Modeling of jitter in bang‐bang clock and data recovery circuits

Jitter and metastability analysis and modeling of multilevel bang‐bang phase detector

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