Summary Voltage‐controlled oscillator (VCO) is the most basic component required for all wireless and communication systems. In this article, a four‐stage differential ring VCO with two control voltages for wide tuning range is proposed. This VCO uses the dual‐delay loop technique for high operation frequency. Also, a low‐VT NMOS transistor is used in series with pull down network of the proposed VCO delay cell to achieve low frequencies. Prelayout simulation of the proposed VCO is performed in 65‐nm TSMC CMOS technology in Cadence software under 1.2‐V supply voltage. The tuning range of the proposed VCO varies from 1 MHz to 13.8 GHz and has been improved by 19.77% compared to other works. The power consumption of this low power VCO is between 29.3 μW to 1.715 mW. The phase noise of the proposed circuit is −82.3 dBc/Hz at 1 MHz offset frequency and −106.9 dBc/Hz at 10 MHz offset frequency from 5.161 GHz center frequency, while its area is 102.457 μm2. This design demonstrates other benefits in low power consumption and area compared with other ring oscillators.

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One of the effective ways to reduce power consumption is using clustered voltage scaling technique. The level converter flip-flop is needed to control static current when the block with Low Supply Voltage (VDDL) drives the block with High Supply Voltage (VDDH). One of the big challenges of design is that level converter flip-flop has low power and high speed. In this paper, pulse triggered level converter flip-flop and double edge pulse generator were proposed. This level converter flip-flop used conditional data mapping technique for reducing power consumption. An explicit double edge pulse generator could be shared among several level converter flip-flops so that power consumption would be reduced. Also, the number of stack transistor was reduced in the discharging path that causes delay decrease. The simulation results showed that the proposed flip-flop reduced 20% of power consumption and 17% of delay in comparison with other flip-flops at 50% data switching activity. consumption at all corners. Waveform of the proposed flip-flop given in Figure 9 demonstrates that input data with low voltage changed to output with high voltage. CONCLUSIONIn this paper, the explicit double edge pulse triggered level converter flip-flop and double edge clock pulse generation were proposed. The proposed flip-flop used conditional data mapping and double edge triggering for reducing power consumption. Also, it reduced the number of stack transistors in discharging path for reducing delay. All the flip-flops were simulated by HSPICE in 65 nm complementary metal-oxide semiconductor technology. The proposed flip-flop reduced 20% of power consumption and 17% of delay in comparison with other flip-flops. 523

A novel fault tolerant delay cell for ring oscillator (RO) is proposed. As RO is one of the crucial blocks in phased locked loop, delayed locked loo and clock data recovery, it should be tolerated against single event transient (SET) and stuck at faults for harsh environment. Their proposed hybrid fault tolerant topology is combination of triple and quad transistors redundancy, which is applied to the delay cell structure based on the sensitivity role of each transistor. The simulation results with Cadence software show that the proposed fault-tolerant delay cell dissipates 34.34 µW power, while it occupies 127.2 µm 2 chip area. The proposed topology not only has lower power dissipation in comparison with existing fault tolerant delay cells but also is more reliable against stuck at single and multiple faults and also SETs. By using the proposed reliable delay cell in the RO, the achieved power dissipation and phase noise are about 249 µW and −96 dBc/Hz, respectively, while higher reliability is achieved in comparison with non-redundant RO s.

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