Low-power pulsed hybrid flip-flop based on a C-element

Rahiminejad, Majid; Saneei, Mohsen

doi:10.1016/j.aeue.2014.04.012

Cited by 5 publications

(5 citation statements)

References 17 publications

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“…The proposed LPRA‐FF design performed very efficient than existing design such as HPTFF [35], HSDMHLFF [39], DEPFF [40], SCCER [41], and DDFF [42] in terms of power delay product (PDP). The PDP is a quantitative measure of the efficiency and a compromise between power dissipation and delay.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Rahiminejad et al [35] presented a hybrid pulse-triggered FF (HPTFF) design with adopting a dynamic front-end stage and a static back-end structure. The basic sampling, keeper circuit, and C-element parts are used to implement the hybrid FF.…”

Section: Problem Definitionmentioning

confidence: 99%

“…The basic sampling, keeper circuit, and C-element parts are used to implement the hybrid FF. From related works [25][26][27][28][29][30][31][32][33][34][35], authors have focused to discuss the SEE effects only, another solution is C-element, which is proposed in [35] to overcome the SEE effects such as SET, and SEU in hybrid FF design. The hybrid pulsed FF, using C-element as a fundamental stage, provides better result to resist switching activity and improves data activity.…”

Section: Problem Definitionmentioning

confidence: 99%

“…1. The existing HPTFF [35] design consists of 18 transistors, but the proposed design required 16 transistors.…”

Section: Proposed Tieff Designmentioning

confidence: 99%

“…1. The existing HPTFF [35] design consists of 18 transistors, butthe proposed design required 16 transistors. Depending on the state of clock(C), the functionality of the proposed LPRA‐FF can be categorised into twophases as evaluation and pre‐charge.…”

Section: Proposed Lpra Circuit Designmentioning

confidence: 99%

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Low power radiation aware transistor level design using tri‐state inverter embedded non‐clock gating technique

Kamalakannan¹,

Venkatachalam²

2019

IET Circuits, Devices & Systems

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The effect of radiation on digital circuits in particularly complementary metal oxide semiconductor (CMOS) technology has been known since many years. The two most important radiation effects are total ionisation dose and single-event effects (SEEs). The complexity of circuit will increase depends on the number of gate inputs, which degrades the radiation to accelerate the total dose levels. The incremental dose level affects the circuit parameter failure, which affects the functionality of logic design. Many authors focus to reduce radiation effects with avoid function loss, but those extra efforts consume more power. In this study, a low power radiation aware circuit design is proposed. First, the physics-based modelling approach is used for compute radiation response of each component in the circuit. Tri-state inverter embedded non-clocked gating technique is proposed to eliminate unwanted latches and disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals. For simulation purpose, the authors applied their proposed technique in flip-flops and make it as more aware of radiation effects and power consumption. The performance of the proposed circuit design is analysed at 16 nm CMOS predictive technology model in terms of power delay product using HSPICE tool.

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