Articles you may be interested inPalladium nanoparticle decorated silicon nanowire field-effect transistor with side-gates for hydrogen gas detection Appl. Phys. Lett.Characteristics of gate-all-around silicon nanowire field effect transistors with asymmetric channel width and source/drain doping concentration J. Appl. Phys. 112, 034513 (2012); 10.1063/1.4745858 Electronic transport characteristics of electrolyte-gated conducting polyaniline nanowire field-effect transistors Appl. Phys. Lett. 95, 013113 (2009); 10.1063/1.3176444Strain-induced transconductance enhancement by pattern dependent oxidation in silicon nanowire field-effect transistors Appl.The oxidation of unintentionally doped p-type silicon nanowires grown by the vapor-liquid-solid ͑VLS͒ method and their integration into top-gated field effect transistors is reported. Dry thermal oxidation of as-grown silicon nanowires with diameters ranging from 20 to 400 nm was carried out at 700 and 900°C with or without the addition of a chlorinated gas source. The oxidation rate was strongly dependent on the as-grown nanowire diameter, with the large-diameter nanowires oxidizing up to five times faster than the smallest nanowires at 900°C. At each diameter, the addition of trichloroethane ͑TCA͒ enhanced the rate compared to oxidation in pure O 2 . Top-gated field effect transistors fabricated from nanowires oxidized at 700°C had significantly less hysteresis in their subthreshold properties when TCA was added, but oxidation at 900°C with or without TCA provided hysteresis-free devices with improved subthreshold slope. Such enhancements in the electrical properties are expected based on advances in planar silicon process technology and emphasizes the importance of incorporating these techniques for VLS-grown nanowire devices.