Phosphine (PH3) was investigated as an n-type dopant source for Au-catalyzed vapor-liquid-solid (VLS) growth of phosphorus-doped silicon nanowires (SiNWs). Transmission electron microscopy characterization revealed that the as-grown SiNWs were predominately single crystal even at high phosphorus concentrations. Four-point resistance and gate-dependent conductance measurements confirmed that electrically active phosphorus was incorporated into the SiNWs during VLS growth. A transition was observed from p-type conduction for nominally undoped SiNWs to n-type conduction upon the introduction of PH3 to the inlet gas. The resistivity of the n-type SiNWs decreased by approximately 3 orders of magnitude as the inlet PH3 to silane (SiH4) gas ratio was increased from 2 x 10(-5) to 2 x 10(-3). These results demonstrate that PH3 can be used to produce n-type SiNWs with properties that are suitable for electronic and optoelectronic device applications.

Axially doped (n+-p--n+) silicon nanowires were synthesized using the vapor-liquid-solid technique by sequentially modulating the introduction of phosphine to the inlet gas stream during growth from a silane source gas. Top-gate and wrap-around-gate metal oxide semiconductor field-effect transistors that were fabricated after thermal oxidation of the silicon nanowires operate by electron inversion of the p- body segment and have significantly higher on-state current and on-to-off state current ratios than do uniformly p- -doped nanowire field-effect devices. The effective electron mobility of the devices was estimated using a four-point top-gate structure that excludes the source and drain contact resistance and was found to follow the expected universal inversion layer mobility versus effective electric field trend. The field-effect properties of wrap-around-gate devices are less sensitive to global-back-gate bias and thus provide better electrostatic control of the nanowire channel. These results demonstrate the ability to tailor the axial doping profile of silicon nanowires for future planar and vertical nanoelectronic applications.

High density, intentionally doped silicon nanowire (SiNW) arrays were fabricated within the pores of anodic alumina (AAO) templates via gold-catalysed vapour–liquid–solid (VLS) growth using silane (SiH4) as the source gas and trimethylboron ((CH3)3B, TMB) and phosphine (PH3) as p-type and n-type dopant sources, respectively. The AAO template serves as a support structure for nanowire growth and fabrication of electrical contacts to the nanowire arrays. Nanowire array resistance was measured as a function of SiNW length for a series of samples prepared with different dopant/SiH4 inlet gas ratios. A method was developed to extract the SiNW resistivity from the measurements of array resistance versus nanowire length. The nanowire resistivity measured from the arrays decreased with increasing dopant/SiH4 ratio and compared favourably with resistivity data obtained from four-point measurements of individual SiNWs grown under identical conditions. Nominally undoped SiNWs grown in the AAO templates were found to be p-type with resistivity in the range of 1–3 Ω cm, indicating the presence of unintentional acceptors in the wires. The resistivity of undoped SiNWs grown under identical conditions but on oxidized (100) Si substrates was much higher, of the order of 104–105 Ω cm, suggesting that the AAO templates are the source of the acceptor impurities.

Articles you may be interested inPalladium nanoparticle decorated silicon nanowire field-effect transistor with side-gates for hydrogen gas detection Appl. Phys. Lett.Characteristics of gate-all-around silicon nanowire field effect transistors with asymmetric channel width and source/drain doping concentration J. Appl. Phys. 112, 034513 (2012); 10.1063/1.4745858 Electronic transport characteristics of electrolyte-gated conducting polyaniline nanowire field-effect transistors Appl. Phys. Lett. 95, 013113 (2009); 10.1063/1.3176444Strain-induced transconductance enhancement by pattern dependent oxidation in silicon nanowire field-effect transistors Appl.The oxidation of unintentionally doped p-type silicon nanowires grown by the vapor-liquid-solid ͑VLS͒ method and their integration into top-gated field effect transistors is reported. Dry thermal oxidation of as-grown silicon nanowires with diameters ranging from 20 to 400 nm was carried out at 700 and 900°C with or without the addition of a chlorinated gas source. The oxidation rate was strongly dependent on the as-grown nanowire diameter, with the large-diameter nanowires oxidizing up to five times faster than the smallest nanowires at 900°C. At each diameter, the addition of trichloroethane ͑TCA͒ enhanced the rate compared to oxidation in pure O 2 . Top-gated field effect transistors fabricated from nanowires oxidized at 700°C had significantly less hysteresis in their subthreshold properties when TCA was added, but oxidation at 900°C with or without TCA provided hysteresis-free devices with improved subthreshold slope. Such enhancements in the electrical properties are expected based on advances in planar silicon process technology and emphasizes the importance of incorporating these techniques for VLS-grown nanowire devices.