A Comparative Performance Analysis of 6T &amp; 9T SRAM Integrated Circuits: SOI vs. Bulk

Khan, Qazi Mashaal; Perdriau, Richard; Ramdani, Mohamed; Koohestani, Mohsen

doi:10.1109/lemcpa.2022.3163963

Cited by 6 publications

(2 citation statements)

References 25 publications

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“…Thus, we have incorporated above said doping profiles for NS-FET. The proposed NS-FET is adopted with silicon-on-insulator (SOI) technology which improves electrostatics, near ideal subthreshold characteristics, minimizes parasitic capacitances, less power consumption and suppressed threshold voltage (Vth) variations [23]. The Genius 3D TCAD simulator by Cogenda [24], is used for the generation and simulation of the JL and INV mode NS-FET structures.…”

Section: Device Description and Simulation Methodologymentioning

confidence: 99%

Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison

Sreenivasulu,

Neelam,

Kola

et al. 2023

IEEE Access

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In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In JL mode, the ION rises with an increase in temperature compared to the downfall trend in INV mode. In addition, compared to JL mode, the INV mode exhibits a better negative temperature coefficient of threshold voltage (dVth/dT). Further, the mixed mode circuit simulations are carried out using the Cadence Virtuoso platform through the Verilog-A model. From the analysis, it is observed that an increase of 20% gain in INV mode compared to JL mode for a common source (CS) amplifier. JL mode NS-FETs achieve higher CMOS inverter switching current (ISC) and lower energy-delay products (EDP) as temperature rises. A three-stage ring oscillator (RO) is designed, and the oscillation frequencies (fOSC) of 43.39 GHz and 38.8 GHz are obtained with INV and JL modes. Although JL NSFET offers less intrinsic capacitances, the fOSC is high for INV mode due to higher ION. Furthermore, reducing supply voltage (VDD), the fOSC falls by 67% with INV and 62.6% with JL modes. These results will give a better understanding of this emerging NS-FET at both device and circuit levels at advanced technology nodes.

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Section: Device Description and Simulation Methodologymentioning

confidence: 99%

Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison

Sreenivasulu,

Neelam,

Kola

et al. 2023

IEEE Access

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“…To see the dependence of the output frequency on temperature, the latter was increased from −40 °C to 120 °C with 5 °C step size and an accuracy of ±1 °C. Although the IC developed in SOI can withstand temperatures up to 175 °C compared to the conventional bulk CMOS technology [37], the mentioned range was selected as it complies with the temperature limit of all the components soldered on the PCB.…”

Section: Effect Of Temperature Variation On the Integrated Oscillatorsmentioning

confidence: 99%

Experimental Characterization of Multitone EM Immunity of Integrated Oscillators Under Thermal Stress

et al. 2022

Self Cite

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The reliable operation of an integrated circuit can be affected by environmental changes, such as of multiple frequency electromagnetic (EM) disturbances and temperature variations. This paper compares the performance of two oscillator circuits, namely a current-starved voltage controlled oscillator and a ring oscillator integrated into a chip, in terms of their immunity to multitone direct power injection while under the influence of thermal stress. The objective is to demonstrate by the means of measurements the synergistic effect caused by multitone EM disturbances in a test chip, in contrast to the conventional single-tone EM disturbances. Moreover, the multitone immunity levels of integrated blocks with different architectures but similar functionality are analyzed at extreme temperature deviations. Bayesian networks (BN) are applied in order to visualize the probability of circuit failure due to multitone disturbances and temperature influence. Additionally, noisy-OR and improved-adaptive-recursive-noisy-OR (I-ARNOR) probabilistic models are implemented to identify the types of causal interactions (i.e. inhibition and positive causality) between multitone disturbances and to predict the probability of failure due to higher order multitone disturbances, respectively.

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Synaptic MIS Silicon Nitride Resistance Switching Memory Cells on SOI Substrate

Mavropoulis,

Vasileiadis,

Normand

et al. 2023

2023 IEEE 23rd International Conference on Nanotechnology (NANO)

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A Comparative Performance Analysis of 6T & 9T SRAM Integrated Circuits: SOI vs. Bulk

Cited by 6 publications

References 25 publications

Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison

Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison

Experimental Characterization of Multitone EM Immunity of Integrated Oscillators Under Thermal Stress

Synaptic MIS Silicon Nitride Resistance Switching Memory Cells on SOI Substrate

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