A comparative performance analysis of CMOS XOR XNOR circuits

Sharma, Trapti; Kumre, Laxmi

doi:10.1109/rise.2017.8378202

Cited by 4 publications

(2 citation statements)

References 20 publications

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“…Several works explore different implementations of the XOR gate. Most of the works investigate new transistor arrangements, for example, presenting comparative evaluations [28] or reduced number of transistors XOR gates, as in [29] that a 2T XOR circuit is proposed, or as in [30] that menristor MOS technology is explored. Few work have observed the behavior of these circuits under critical situations, as for example low power operation [31,32], radiation environments [10] or the nanometer variability effects [33,9].…”

Section: Xor Gatesmentioning

confidence: 99%

Soft Error Impact on FinFET and CMOS XOR Logic Gates

Oliveira

Meinhardt

2020

JICS

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With the advance of computer systems, XORgates design became essential on arithmetic circuits.Atnanometer nodes, despite the electrical characterization, de-signers must to consider soft error impact on the circuits. Thechallenges change significantly as feature size are smaller, evenfor FinFET devices. The effects of Single Event Transientare dependent of the circuit topology. Thus, in this work, weevaluate the influence of nine XOR topologies on the radia-tion robustness, discussing the influence of logic family, the de-vice technology and environment factors as temperature, onthe radiation robustness. Also, this work explore the nominaland near-threshold operation of these XOR topologies. Resultsshows that FinFET devices are significantly more robust to theradiation effects. Also, most of PTL logic XORs topologiespresent about 40% of increase on the LET threshold. The de-pendence of temperature aggressively impact the FinFET tech-nology devices operating at near-threshold. Finally, the com-plete set of information provided in this work support design-ers to choose the most appropriate XOR topology accordingthe specific design requirements.

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Section: Xor Gatesmentioning

confidence: 99%

Soft Error Impact on FinFET and CMOS XOR Logic Gates

Oliveira

Meinhardt

2020

JICS

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“…Vários trabalhos exploram diferentes implementações de uma função lógica XOR, investigando novos arranjos de transistores, utilizando novas tecnologias e observando o comportamento desses circuitos em situações críticas, como por exemplo operação de baixa potência, ambientes de radiação ou projetos de nanotecnologias e seus desafios atuais [9,10,13,15,18,21,23,29]. Entretanto, a maioria destes trabalhos considera apenas a tecnologia CMOS ou FinFET, dificultando a análise comparativa devido às diferenças na configuração experimental.…”

Section: Introductionunclassified

Análise do Comportamento Elétrico e da Robustez à Radiação de Circuitos XOR em Tecnologia Nanométrica FinFET

Oliveira

Meinhardt

2020

Anais Do XI Computer on the Beach - COTB '20

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Electronic circuits are becoming more susceptible to errorscaused by radiation due to scaling down technological nodeand high operating frequencies [4, 5, 11].This work presentsa comparative analysis of the sensitivity radiation fordifferent XOR gate topologies 16 nm. The doors wereimplemented considering two different devices:Complementary Metal-Oxide Semiconductor (CMOS bulk)and Fin Field-Effect Transistor (FinFET) and two logics:Complementary Logic (CMOS logic) and Logic PassageTransistor (PTL). To allow a more detailed comparison, thiswork also discusses the critical delay results, power and thePower-Delay Product (PDP), a metric that defines thepower dissipated by the circuit to perform an operation, foreach version of XOR. The doors PTL-based XORs showedsuperior improvements 13% for the critical delay and 11%for the PDP in relation to CMOS logic. The topologies of thePTL family still showed greater robustness against the effectsof radiation when compared to ports implemented withCMOS logic, with a Linear Energy Transfer (LET) beingalmost 30% higher for CMOS devices and approximately20% higher for FinFET devices. In addition, circuits basedon FinFET are about 70% faster, have a PDP 80% smallerand are approximately 300x more robust than CMOStechnology, with an improvement in the LET threshold ofboth logical families evaluated.

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Design-Space Exploration of Conventional/Non-conventional Techniques for XOR/XNOR Cell

Sharma,

Jhamb

2023

Lecture Notes in Electrical Engineering

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A comparative performance analysis of CMOS XOR XNOR circuits

Cited by 4 publications

References 20 publications

Soft Error Impact on FinFET and CMOS XOR Logic Gates

Soft Error Impact on FinFET and CMOS XOR Logic Gates

Análise do Comportamento Elétrico e da Robustez à Radiação de Circuitos XOR em Tecnologia Nanométrica FinFET

Design-Space Exploration of Conventional/Non-conventional Techniques for XOR/XNOR Cell

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