Design-Space Exploration of Conventional/Non-conventional Techniques for XOR/XNOR Cell

Sharma, Uma; Jhamb, Mansi

doi:10.1007/978-981-99-4495-8_27

Cited by 2 publications

(1 citation statement)

References 35 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As compared to FGMOS-NAND gate, it offers 14.68× (depicted in figure 10(a)) reduced propagation delay. Also, power consumption of FG-CNTFET technology is much lesser than the FGMOS technology [37,38].…”

Section: Conclusion and Future Scopementioning

confidence: 99%

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Sharma,

Jhamb

2024

Eng. Res. Express

Self Cite

View full text Add to dashboard Cite

Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442nW and 0.323nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.

show abstract

Section: Conclusion and Future Scopementioning

confidence: 99%

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Sharma,

Jhamb

2024

Eng. Res. Express

Self Cite

View full text Add to dashboard Cite

show abstract

Exploring supply voltage and temperature variation on XOR-XNOR cells with conventional/non-conventional techniques

Sharma,

Jhamb

2024

Facta Univ Electron Energ

View full text Add to dashboard Cite

This paper delves into a comprehensive exploration of conventional and unconventional design approaches applied in XOR-XNOR cells. These cells play a crucial role in various arithmetic logic circuits with substantial computational capacity within VLSI designs operating at low voltage and power levels. The paper investigates the difficulties linked with both conventional and non-conventional design strategies. Furthermore, it performs a relative evaluation of different XOR/XNOR cells documented in current literature concerning circuit design parameters. The results of this investigation indicate that the adoption of carbon nanotube field-effect transistor (CNTFET) technology in lower technology nodes significantly decrease circuit delay, while floating gate metal-oxide semiconductor (FGMOS) technology displays superior interpretation in terms of circuit power efficiency. The discussion also covers the utilization of FinFET technology in the creation of XOR/XNOR cells. This paper conducts an assessment of the voltage and temperature resilience of these XOR/XNOR cells. The analysis has been undertaken utilizing the HSPICE tool at 22nm technology node. The XOR/XNOR cell based on FGMOS demonstrates the highest resilience to voltage and temperature fluctuations. The major challenges encountered in the adoption of nonconventional technologies involve the lack of appropriate simulation models and the intricate fabrication processes. These challenges notably hinder the progress and adoption of these pioneering methodologies.

show abstract

Design-Space Exploration of Conventional/Non-conventional Techniques for XOR/XNOR Cell

Cited by 2 publications

References 35 publications

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Exploring supply voltage and temperature variation on XOR-XNOR cells with conventional/non-conventional techniques

Contact Info

Product

Resources

About