2018 2nd International Conference on Electronics, Materials Engineering &Amp; Nano-Technology (IEMENTech) 2018

DOI: 10.1109/iementech.2018.8465371

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A Comparative Study of Arithmetic Multipliers

Uditnarayan Mandal

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Rigjit Banerjee

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Cited by 4 publications

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Configurable DSI partitioned approximate multiplier

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et al. 2021

Future Generation Computer Systems

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No abstract

Configurable DSI partitioned approximate multiplier

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et al. 2021

Future Generation Computer Systems

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No abstract

Low Powered Self-Testable ALU

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2021

IOP Conf. Ser.: Mater. Sci. Eng.

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The Arithmetic and Logic Unit(ALU) is a Significant Segment of a CPU as it does all the arithmetic and logical operations and computations required by all the processes running inside the CPU. Being such an important part inside the processor, It requires more power and thus it would be efficient and feasible if it can run on low power and also can test for any faults in the circuit itself. This paper completely focuses on building a Low Powered ALU with the implementation of Built-In Self-Test(BIST) mechanism for efficient arithmetic and logical operations. In the design, power-efficient circuits such as Wallace Tree Multiplier and Carry Look-Ahead Adder is being used. The created design is synthesized and simulated on the Xilinx Vivado software tool and implemented on Digilent Xilinx Basys 3 Artix-7 (XC7A35T-1CPG236C) Field Programmable Gate Array (FPGA). The overall power consumption of the design is 75mW and the ALU has self-testability function.

Implementation of ALU using RTL to GDSII flow and on NEXYS 4 DDR FPGA board

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2021

2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC)

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