A comparative study of gate direct tunneling and drain leakage currents in n-MOSFET's with sub-2 nm gate oxides

Yang, Ni; Henson, W.K.; Wortman, J. J.

doi:10.1109/16.853042

Cited by 97 publications

(54 citation statements)

References 28 publications

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“…As with joint device sizing and supply and threshold voltage optimization, GP-based design can be carried out with multiple doping concentrations, channel lengths and oxide thicknesses, because models of gate delay as a function of doping concentration, channel length, and oxide thickness, as well as the device width, supply, and threshold voltage, can be well approximated as generalized posynomials. The models described in Bowman et al (2001), Lindert et al (1999), Yang et al (2000), and Sirisantana and Roy (2004), for example, are all (approximately) compatible with GP-based design.…”

Section: P -P|mentioning

confidence: 85%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Section: P -P|mentioning

confidence: 85%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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“…Bei der 65 nm Technologie beträgt die Gateoxiddicke eines MOS Transistors weniger als 2 nm, gemäß der Skalierungsregeln. Durch diese zunehmende Verkleinerung der Oxidschicht beginnen die Tunnelströme exponentiell zu wachsen (Yang, 2000). Dies bedeutet, dass bei Schaltungen, die nanoskalierten MOS-Bauelementen enthalten, eine Zunahme von parasitären Strömen zu erwarten ist, welche die Funktionsweise signifikant beeinflussen.…”

Section: Introductionunclassified

Das Verhalten nanostrukturierter Schaltungen unter der Berücksichtigung von Quanteneffekten

et al. 2006

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Zusammenfassung. Aufgrund der Bedeutung der MOSTechnologie für die Halbleiterindustrie und deren fortschreitende Miniaturisierung ist es wichtig sicherzustellen, dass die klassischen Schaltungskonzepte für stark skalierte Bauelemente nicht ihre Gültigkeit verlieren. Ziel unserer Arbeitsgruppe ist es ein Simulatorpaket zu entwickeln, welches von einer physikalischen Sicht heraus quantenmechanische Einflüsse in integrierten Schaltungen ermittelt und Konsequenzen für zukünftiges Schaltungsdesign prognostiziert. Zur Berechnung und Modellierung der Quanteneffekte wird ein auf dem "non equilibrium Green's functions" (NEGF) Formalismus basierender numerischer 1-dimensionaler Simulator entwickelt. Auf der Basis von numerischen Transportsimulationen werden Ersatzschaltbilder für die SPICE Simulationsumgebung erstellt, um den Einfluss der Quanteneffekte in die Schaltungssimulation einzubinden.Abstract. In this paper we discuss the expected impact of quantum effects in nanostructured CMOS circuits. In order to describe transport in mesoscopic electronic systems our group develops a 1-d numerical simulation packet based on the "non equilibrium Green's functions" (NEGF) formalism. By means of the obtained simulation results we develop extended SPICE circuit models. With these SPICE models the influence of quantum effects to the functionality of classical circuit concepts can be studied. Using these results it is our intention to develop circuits with a higher robustness against these quantum effects. For the illustration of our simulation concept we discuss some results of some circuit examples.

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“…In every iteration, the SAT solver produces many conflict clauses during the search for the answer. 1 We use this fact to speedup the search by using the conflict clauses that are generated during the i th iteration and adding new clauses to them to model the (i+1) th iteration. This is instrumental in substantially decreasing the computation time.…”

Section: Finding the Minimum Leakage Vectormentioning

confidence: 99%

“…In other words, if we must have a "1" at the output of the gate when in 1 Conflict arises when during the search one or more clauses become unsatisfiable in the current search sub-space. The SAT algorithm backtracks from this point and also learns form the conflict by adding one or more conflict clauses to its database.…”

Section: Leakage Reduction By Adding Control Pointsmentioning

confidence: 99%

“…Consequently, estimation and control of subthreshold leakage current in CMOS circuits are important issues, especially in low power applications. On the other hand in the thin gate-oxide regime gate tunneling current between the gate and the source-drain extension overlap region, known as edge direct tunneling and between the gate and the channel becomes considerable in the total "off" state leakage current of the transistor [1]. The contribution of gate leakage to the total leakage is expected to increase in future technology generations [2].…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits

Abdollahi

Fallah

Pedram

Sixth International Symposium on Quality of Electronic Design (ISQED'05)

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Abstract-We show that leakage current in VLSI circuits is not only a function of the current state (input combination) of a combinational circuit but also is dependent on the state history (previous input combinations.) As an example application of the transition-dependent leakage model, we extend a known technique for calculating and applying the minimum leakage input vector to a combinational circuit in the standby mode to one which calculates and applies a pair of input vectors to initialize the circuit to the minimum leakage configuration.

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A comparative study of gate direct tunneling and drain leakage currents in n-MOSFET's with sub-2 nm gate oxides

Cited by 97 publications

References 28 publications

Digital Circuit Optimization via Geometric Programming

Digital Circuit Optimization via Geometric Programming

Das Verhalten nanostrukturierter Schaltungen unter der Berücksichtigung von Quanteneffekten

Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits

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