A comparative study of NEGF and DDMS models in the GAA silicon nanowire transistor

Hosseini, Reza; Fathipour, Morteza; Faez, Rahim

doi:10.1080/00207217.2012.669709

Cited by 12 publications

(7 citation statements)

References 14 publications

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“…The classical models of simulation are optimal for bulk devices but for mesoscopic and nanoscopic electronic devices, quantum mechanical models are required. For L ch < 15 nm, the conduction in channels behaves at near ballistic limits, and the generation of the electron-hole pairs is governed by the band-to-band tunneling despite thermal effects and hence displays quantum effects [ 34 ]. The atomicity/molecularity of the device alters the quantum behavior, which affects the potential of the system.…”

Section: Computational Modeling and Methodologymentioning

confidence: 99%

Effects of Channel Length Scaling on the Electrical Characteristics of Multilayer MoS2 Field Effect Transistor

et al. 2023

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With the rapid miniaturization of integrated chips in recent decades, aggressive geometric scaling of transistor dimensions to nanometric scales has become imperative. Recent works have reported the usefulness of 2D transition metal dichalcogenides (TMDs) like MoS2 in MOSFET fabrication due to their enhanced active surface area, thin body, and non-zero bandgap. However, a systematic study on the effects of geometric scaling down to sub-10-nm nodes on the performance of MoS2 MOSFETs is lacking. Here, the authors present an extensive study on the performance of MoS2 FETs when geometrically scaled down to the sub-10 nm range. Transport properties are modelled using drift-diffusion equations in the classical regime and self-consistent Schrödinger-Poisson solution using NEGF formulation in the quantum regime. By employing the device modeling tool COMSOL for the classical regime, drain current vs. gate voltage (ID vs. VGS) plots were simulated. On the other hand, NEGF formulation for quantum regions is performed using MATLAB, and transfer characteristics are obtained. The effects of scaling device dimensions, such as channel length and contact length, are evaluated based on transfer characteristics by computing performance metrics like drain-induced barrier lowering (DIBL), on-off currents, subthreshold swing, and threshold voltage.

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Section: Computational Modeling and Methodologymentioning

confidence: 99%

Effects of Channel Length Scaling on the Electrical Characteristics of Multilayer MoS2 Field Effect Transistor

et al. 2023

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“…Due to the symmetry of the cylindrical structure, a 2d cylindrical mesh has been applied to avoid computational complexity. At sub-10 nm structure, the source to drain tunneling can not be ignored and the strong quantum confinement effects in nanowire should be considered [29]. The NEGF_MS is a full quantum transport model that includes the source to drain tunneling, ballistic transport, and quantum transport [30].…”

Section: Device Structure and Methodologymentioning

confidence: 99%

“…For the HGO-CPNWT, the barrier height near the source-channel region is higher compared to the other two structures because of the high-κ dielectric oxide at the source side. This results in a low off-state current because of the increased barrier height and also due to the back-scattering event of the electrons [29]. The barrier height is also higher for the SGO-CPNWT compared to the CCPNWT.…”

Section: Characteristicsmentioning

confidence: 99%

Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

Debnath,

Sikder,

Singha

2023

Eng. Res. Express

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In this work, a Hetero-Gate-Oxide Charge Plasma-based Nanowire Transistor (HGO-CPNWT) has been proposed, characterized, and a comparative analysis with the Conventional Charge Plasma-based Nanowire Transistor (CCPNWT) and the Stack-Gate-Oxide CPNWT (SGO-CPNWT) has been investigated. The effects of stacking a high-κ gate oxide with a low-κ gate oxide beneath the gate and segmenting the gate oxide with a high-κ oxide at the source side and low-κ oxide at the drain side have been analyzed with the short channel effects (SCEs) parameters and radio-frequency (RF) / analog figure of merits have been analyzed. The HGO-CPNWT demonstrates enhanced performances in terms of Ion/Ioff of 1.66×108, subthreshold slope (SS) of 65.74 mV/decade, drain induced barrier lowering (DIBL) of 47.857 mV/V, peak transconductance (gm) of 3.43×10-5 S/μm, and peak cut-off frequency (ft) of 114 GHz. The simulation employs a comprehensive quantum transport model (NEGF), and the comparative impacts of adjusting channel length (Lg), nanowire radius (r), and gate oxide thickness (Tox) are studied.

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“…Once convergence is achieved, the current is computed. 28,29,31 Probability of electron scattering is almost vanished in silicon transistors with a channel length smaller than 45 nm; 32,33 consequently, ballistic transport model is used in our simulations. Since Von Neumann boundary condition ensures the charge neutrality for ballistic devices in the source and drain regions, this condition is considered both in the source and the drain.…”

Section: Simulation Methodsmentioning

confidence: 99%

Junctionless Field Effect Diode (JL-FED): A First-Principles Study

Vadizadeh¹

2019

ECS J. Solid State Sci. Technol.

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This paper proposes a novel field effect diode (FED) for the first time namely junctionless FED (JL-FED). Our simulation results show that JL-FED gives the combined advantages of conventional FED and JL field effect transistor (JL-FET). In fact, not only fabrication process of the JL-FED is easier than FED, but also unlike a FED, JL-FED device turns on without applied biases to the control gates. Furthermore, to reduce the leakage current of the JL-FED structure, we propose modified JL-FED (MJL-FED) structure, in which the control gates work functions are different from that of JL-FED. The digital performance parameters such as ION/IOFF ratio and subthreshold slope (SS) for MJL-FED are investigated using 2-D simulations. MJL-FED offers superior ION/IOFF ratio and SS than its JL-FED counterpart having same dimensions. Our simulation results show that MJL-FED provides channel length scaling possible down to 10 nm, and it is a reasonable candidate for logic transistor applications.

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A comparative study of NEGF and DDMS models in the GAA silicon nanowire transistor

Cited by 12 publications

References 14 publications

Effects of Channel Length Scaling on the Electrical Characteristics of Multilayer MoS2 Field Effect Transistor

Effects of Channel Length Scaling on the Electrical Characteristics of Multilayer MoS2 Field Effect Transistor

Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

Junctionless Field Effect Diode (JL-FED): A First-Principles Study

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