Advancement in the semiconductor industry has transformed modern society. A
miniaturization of a silicon transistor is continuing following Moore?s
empirical law. The planar metal-oxide semiconductor field effect transistor
(MOSFET) structure has reached its limit in terms of technological node
reduction. To ensure the continuation of CMOS scaling and to overcome the
Short Channel Effect (SCE) issues, a new MOS structure known as Fin
field-effect transistor (FinFET) has been introduced and has led to
significant performance enhancements. This paper presents a comparative
study of CMOS gates designed with FinFET 10 nm, 7 nm and 5 nm technology
nodes. Electrical parameters like the maximum switching current ION, the
leakage current IOFF, and the performance ratio ION/IOFF for N and P FinFET
with different nodes are presented in this simulation. The aim and the
novelty of this paper is to extract the operating frequency for CMOS
circuits using Quantum and Stress effects implemented in the Spice
parameters on the latest Microwind software. The simulation results show a
fitting with experimental data for FinFET N and P 10 nm strctures using
quantum correction. Finally, we have demonstrate that FinFET 5 nm can reach
a minimum time delay of td=1.4 ps for CMOS NOT gate and td=1 ps for CMOS NOR
gate to improve Integrated Circuits IC.