A comparative study on performance and reliability of 32-bit binary adders

Bahadori, Milad; Kamal, Mehdi; Afzali-Kusha, Ali; Pedram, Massoud

doi:10.1016/j.vlsi.2015.12.002

Cited by 10 publications

(5 citation statements)

References 51 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As shown in Figure 4, the SKA reduces the delay in calculating the intermediate prefixes. However, its fan-out will increase at each stage [9].…”

Section: Sklansky Addermentioning

confidence: 99%

Design and Implementation of RISC-V Based Pipelined Multiplier

Sun,

Liu,

Zhang

et al. 2023

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

Among the many microprocessors, RISC-V as an open-source instruction set is gradually gaining popularity among academia and industry. The performance of the multiplier in the microprocessor imposes constraints on the computational power of the processor. In order to improve the efficiency of multiplication instructions, a pipeline multiplier is implemented in this paper. Firstly, the partial product is generated using the Radix-4 booth. Secondly, the Wallace tree structure is used to accelerate the compression of the partial product. Then, a parallel prefix adder is used to calculate the resulting partial product to improve the timing. Finally, registers are added as a pipeline to achieve a high-efficiency multiplication calculation. With the operating voltage and temperature set to typical conditions, the integrated multiplier area is 50260.6 μm2, and the power consumption is 20.41 mW. The final frequency of the multiplier is 1 GHz in gate-level simulation.

show abstract

“…As shown in Figure 4, the SKA reduces the delay in calculating the intermediate prefixes. However, its fan-out will increase at each stage [9].…”

Section: Sklansky Addermentioning

confidence: 99%

Design and Implementation of RISC-V Based Pipelined Multiplier

Sun,

Liu,

Zhang

et al. 2023

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

show abstract

“…The parallel adders, based on CMOS have variation in delay, power consumption and PDP as, on average, 3%, where as in full swing GDI based, the variations are approximately about 1. Adder Efficiency: An approach of comparing different adders by defining Merit Factor (MF) based on the performance and the reliability parameters is discussed in [1]. The speed and energy consumption are the key parameters for determining the efficiency of the adders design, so the product of delay and power are considered as the merit factor.…”

Section: Csla_convmentioning

confidence: 99%

“…High power consumption raises temperature profile of the chip and affects overall performance of the system. Moreover, the explosive growth in laptops and portable personal communication systems demand long 1 Manuscript received 12 June 2016. Received in revised form 27 May 2017.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic

Mohan¹,

Nakkeeran²

2017

ELS

View full text Add to dashboard Cite

In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation withi one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate and carry propagate adder. They are implemented with using full swing GDI logic. Due to their reduced transistor count and less power consumption, this multiplier implementation leads to significant improvement compared with the existing implementations. The designed and existing array multipliers are simulated at 45 nm technology model and their power consumption and delay are calculated from the simulation results. It is validated that the proposed hierarchy array multiplier based on full swing GDI logic has 27% less energy consumption than the existing design. The results confirmed that implemented multiplier has shown better performance and can be used for signal and im age processing.

show abstract

“…5 During the process of attempting to improve transistor performance, the double-gated transistors showed good potential towards improving the switching strength and hence the performance of the transistor. [6][7][8][9][10][11] Despite this improvement, the new structure introduced different types of dimensional variability. Thus, process variation continued to be one of the main challenges for design reliability.…”

Section: Introductionmentioning

confidence: 99%

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

Majzoub¹,

Taouil²,

Hamdioui³

2019

Journal of Low Power Electronics

View full text Add to dashboard Cite

Standard low power design utilizes a variety of approaches for supply and threshold control to reduce dynamic and idle power. At a very early stage of the design cycle, the V dd and V th values are estimated, based on the power budget, and then used to scale the delay and estimate the design performance. Furthermore, process variation in sub-20 nm feature technologies introduces a substantial impact on speed and power. Thus, the impact of such variation on the scaled delay has to also be considered in the performance estimation. In this paper, we propose a system-level model to estimate this delay, taking into consideration voltage scaling under within-die process variation for both planar and FinFET CMOS transistors in the sub-20 nm regime. The model is simple, has acceptable accuracy and is particularly useful for architectural-level simulations for lowpower design exploration at an early stage in the design space exploration. The proposed model estimates the delay in different supply voltage and threshold voltage ranges. The model uses a modified alpha-power equation to measure the delay of the critical path of a computational logic core. The targeted technology nodes are 14 nm, 10 nm, and 7 nm for FinFETs, and 22 nm, and 16 nm for planar CMOS. Within-die process variation is assumed to be lumped in with the threshold voltage and the transistor channel length and width to simplify its impact on delay. For the given technology nodes, the average percentage error numbers of theproposed delay equation compared to hSpice are between 0.5% to 14%.

show abstract

A comparative study on performance and reliability of 32-bit binary adders

Cited by 10 publications

References 51 publications

Design and Implementation of RISC-V Based Pipelined Multiplier

Design and Implementation of RISC-V Based Pipelined Multiplier

An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

Contact Info

Product

Resources

About