A comparative study up to 1024 bit Euclid's GCD algorithm FPGA implementation and synthesizing

Al‐Haija, Qasem Abu; Al-Ja'fari, Monther; Smadi, Mahmoud A.

doi:10.1109/icedsa.2016.7818535

Cited by 11 publications

(4 citation statements)

References 3 publications

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“…Dengan metode digital pulse with modulation, besar kecilnya torka dipengaruhi oleh arus, besar kecilnya arus didapatkan dari masukan tegangan. Metode tersebut menggabungkan blok khusus berfrekuensi tinggi yang terdapat pada FPGA seperti delay locked-loop yang dapat mengkalikan frekuensi clock [3]. Pengoperasian SRM menggunakan konverter asimetris tiga fasa untuk melakukan proses eksitasi dan dibantu dengan rotary encoder sebagai pembaca posisi rotornya.…”

Section: Pendahuluanunclassified

Kendali Kecepatan Switched Reluctance Motor Berbasis FPGA

Wibisono

Riyadi

Sulaiman

2022

protk

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Renewable drive technology is developing in the current era, one of which is electric transportation. The Switched Reluctance Motor (SRM) was chosen for the transportation development because it has many advantages, including not using permanent magnets and simple construction in the form of an iron core in the rotor and stator windings. SRM works based on the reluctance phenomenon, namely, if the stator is energized, the stator will attract the nearby rotor, this is based on the tendency of the rotor poles to align with the stator excitation poles. SRM requires high speed switching control to operate and requires correct rotor position to operate. Maximum switching and good accuracy can use Field-Programmable Gate Array (FPGA) and rotary encoder as input for rotor position information. To use SRM in electric transport, it is necessary to adjust the speed with ease and precision. With the Pulse Width Modulation (PWM) technique, the size of the excitation depends on the size of the current, the size of the current is determined by the input voltage to the SRM. In this control, the PWM width can be changed by setting the carrier set and modulation set in the FPGA program. In this study, it is proposed to control the SRM speed by adjusting the PWM of the rotary encoder to produce the desired RPM. To support the achievement of this research, hardware testing was carried out in the laboratory.

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Section: Pendahuluanunclassified

Kendali Kecepatan Switched Reluctance Motor Berbasis FPGA

Wibisono

Riyadi

Sulaiman

2022

protk

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“…Euclidian algorithm [6] is simple well-known iterative method to calculate GCD. Suppose a and b are both integer numbers and > , if not exchange between a and b.…”

Section: Euclidian Algorithmmentioning

confidence: 99%

“…For instance, Q. A. Al-Haija, M. Al-Ja'fari and M. Smadi [6] targeted Altera Cyclone IV FPGA family to design an efficient GCD (Greatest Common Divisor) coprocessor based on Euclid's method with variable datapath sizes. They tested their design using seven FPGA chip technologies in terms of maximum frequency and critical path delay of the coprocessor.…”

Section: Introductionmentioning

confidence: 99%

Reviewing and Analyzing Efficient GCD/LCM Algorithms for Cryptographic Design

Marouf¹,

Asad²

2017

IJNCAA

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In this paper, we provide a practical review with numerical example and complexity analysis for greatest common divisor (GCD) and Least Common Multiple (LCM) algorithms that are commonly used in the computing coprocessors design such as Cryptoprocessor design. The paper discusses four common GCD algorithms: Dijkstra's algorithm, Euclidian algorithm, Binary GCD algorithm, Lehmer's algorithm, and two LCM algorithms: LCM based Prime Factorizations algorithm and LCM based GCD reduction. It was found that Lehmer's algorithm can be used efficiently to compute GCD and LCM with time complexity of ( ( ) ) which enhances the linear time ( ( )) complexity of well-known Euclidian algorithm.

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“…Almost all arithmetic operations are constructed mainly from addition operation. It contributes in almost every processors task to do complex computations such as the random number generators [6] and computation of greatest common divisor [7]. Also, in building cryptographic coprocessor as in elliptic curve cryptographic (ECC) design [8], low power applications [9] as in the tiny RSA Cryptoprocessor design [10], communication systems as in the MIMO System design in [11] and many other applications.…”

Section: Introductionmentioning

confidence: 99%

Fpga Synthesis and Validation of Parallel Prefix Adders

Al‐Haija¹,

Asad²,

Marouf³

et al. 2019

Acta electron. Malays.

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The main objective of this paper is to attain the best achievable time delay reduction with better performance (i.e. frequency) running on FPGA platforms and prove their applicability in high performance reconfigurable computing in addition to evaluate the FPGA design area and thermal power dispassion. The paper presents description on the implementation of five fast radix-2 parallel prefix adders, namely: Ladner-Fischer Adder (LFA), Brent-Kung Adder (BKA), Kogge-Stone Adder (KSA), Hans-Carlson Adder (HCA), and Sklansky Adder (SkA), with variable data path sizes ranging from 8 bits to 64 bits. The PPA topologies were implemented using VHDL description language and synthesized using Altera Cyclone IV E (EP4CE115 F29C7) FPGA chip device. Intensive tests and verifications were conducted and analyzed validate and evaluate the design cost factors: total path delay time, maximum frequency, design area and the total FPGA thermal power dissipations of the FPGA design as well as the hardware utilization. The results on the code synthesizing demonstrated that the proposed FPGA implementation of KSA has recorded the best values of critical path delay with 4.504 ns for 64 bits while BKA recorded the least design area results with 223 logic elements for the same bit length. In terms of power dissipation, KSA and SkA adders have recorded the best outcomes since they consume the minimum total thermal power dissipation among all other PPAs and for all bit lengths. Thus, the performance of the proposed PPA adders was benchmarked against other state-of-the-art designs which results reflected its superiority in terms of throughput of two or more multiple times as compared to others.

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A comparative study up to 1024 bit Euclid's GCD algorithm FPGA implementation and synthesizing

Cited by 11 publications

References 3 publications

Kendali Kecepatan Switched Reluctance Motor Berbasis FPGA

Kendali Kecepatan Switched Reluctance Motor Berbasis FPGA

Reviewing and Analyzing Efficient GCD/LCM Algorithms for Cryptographic Design

Fpga Synthesis and Validation of Parallel Prefix Adders

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