“…To our knowledge, the place-and-route results on several Xilinx FPGA devices of our designs improved both the computation time and the area-time tradeoff of all the hardware pairing coprocessors previously published in the open literature [28,29,1,30,19,32,41,40,39,7,43,10,25]. We are also currently applying the same methodology used in this work to design a coprocessor for the Tate pairing over F 2 m , with promising preliminary results.…”