A comparison of three rounding algorithms for IEEE floating-point multiplication

This paper presents a delay-optimized floating point fused addsubtract (FAS) unit. A FAS unit is very useful for FFT and DCT butterfly operations since it can perform addition and subtraction of two floating point numbers simultaneously. The latency of critical path is reduced by using injection-based rounding method and performing parallel exponent adjustment. The proposed FAS is modeled in Verilog-HDL and synthesized using TSMC 65 nm technology library. Synthesis results show that the proposed FAS requires roughly 60% area of two discrete adders. Comparison results show that our proposed FAS unit is 30% faster and 56% less area than the fastest FAS in previous work.

Section: Introductionmentioning

confidence: 99%

Delay-optimized floating point fused add-subtract unit

Wang

Zuo

2015

“…To decrease the area, the injection-base rounding algorithm is used and improved. According to [14], the injection signal should have 24 bits. By analyzing, we found that 3 or 5 bits are enough to store the value of the injection.…”

Section: Implementation and Techniquesmentioning

confidence: 99%

“…To keep the delay as small as possible, we used the injection-based [14] rounding method. In our proposed structure, the guard, round and sticky bit of FAR path is in position 0(g1), À1ðr1Þ and À2ðs1Þ for case I and II; and in position À2ðg0Þ, À3ðr0Þ and À4ðs0Þ for case III and IV, shown in Fig.…”

Section: Implementation and Techniquesmentioning

confidence: 99%

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A two-item floating point fused dot-product unit with latency reduced

Wang

Liu

et al. 2016

This paper presents a floating point fused dot-product (FDP) unit with latency reduced. The proposed FDP unit performs the dot-product operation of four floating point numbers: ab ² cd and is implemented with dual-path algorithm. The proposed FDP is modeled in Verilog-HDL and synthesized using TSMC 65 nm technology library. Synthesis results show that our proposed FDP unit is 24∼30% faster and 36.4% less area than the fastest FDP in previous work. We also use the proposed FDP unit and our previously designed FAS (fused add-subtract) unit to implement a FFT Radix-2 Butterfly (R2BF) unit. The latency of our proposed R2BF unit is improved roughly by 34% and the area is reduced by 41.6%, compared to the fastest 2's-complement butterfly unit.

“…When performing two single precision multiplications, the multiplier uses two rounder units in parallel. For performance reasons, rounding is preferably executed in parallel with carry propagate addition step [13]. Fig.…”

Section: Roundermentioning

confidence: 99%

An efficient floating-point multiplier for digital signal processors

Liu

Guo

2014

Abstract:The floating-point multiplication is one of the most basic and frequent digital signal processing operations, and its accuracy and throughput greatly decide the overall accuracy and throughput of the digital signal processors. Based on vectorizing a conventional double precision multiplier, we propose a multiple precision floating-point multiplier. It supports either one double precision multiplication for high accuracy or two parallel single precision multiplications for high throughput. The evaluation results show that the proposed multiplier is suitable for embedded DSPs. It consumes 8.9% less area than two single precision multipliers. Compared the configuration with a single precision multiplier and a double precision multiplier, the proposed multiplier consumes 30.1% less area.