An efficient floating-point multiplier for digital signal processors

Abstract

Abstract:The floating-point multiplication is one of the most basic and frequent digital signal processing operations, and its accuracy and throughput greatly decide the overall accuracy and throughput of the digital signal processors. Based on vectorizing a conventional double precision multiplier, we propose a multiple precision floating-point multiplier. It supports either one double precision multiplication for high accuracy or two parallel single precision multiplications for high throughput. The evaluation results show that the proposed multiplier is suitable for embedded DSPs. It consumes 8.9% less area than two single precision multipliers. Compared the configuration with a single precision multiplier and a double precision multiplier, the proposed multiplier consumes 30.1% less area.

Design of low-power low-area asynchronous iterative multiplier

“…Various strategies have been devoted to decreasing the power of different type of multipliers [1,2,3,4,5,6,7,8,9,10]. Some of them are briefly introduced below.…”