A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture

Abstract

The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs to be programmed in hardware description or assembly languages, whereas most application programmers are familiar with the algorithmic programming paradigm. SA-C has been proposed as an expression-oriented language designed to implicitly express data parallel operations. Morphosys is a reconfigurable system-on-chip architecture that supports a data-parallel, SIMD computational model. This paper describes a compiler framework to analyze SA-C programs, perform optimizations, and map the application onto the Morphosys architecture. The mapping process involves operation scheduling, resource allocation and binding and register allocation in the context of the Morphosys architecture. The execution times of some compiled image-processing kernels can achieve up to 42x speed-up over an 800 MHz Pentium III machine.

Highly Expandable Reconfigurable Platform using Multi-FPGA based Boards

“…Both FPGAs are connected directly with each other through a high speed bus for fast transferring of data. There are two dedicated DMA (Direct Memory Access) controllers [15] Therefore to avoid wastage of resources configurator is a removable device. Task of controller in the configurator is to control configuring and reconfiguring operations of FPGAs through ROMs.…”

A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures

“…[4], [3], and [5] are another noticeable works related to ours. However, their target machines are different from ours in that our RSPA model supports common resource sharing for heavy computation like multiplication and increase performance using loop pipelining, so their mapping algorithms are not able to be directly applied to our RSPA for maximized performance.…”

Non-intrusive dynamic application profiler for detailed loop execution characterization

“…Application profiling is often utilized to determine an application's frequently executed regions, or critical kernels. Partitioning these critical kernels to hardware has been shown to provide application speedups of 10-100X [14][17] [22] [25]. Such approaches are effective because many software applications follow the 90-10 rule of thumb that states 90% of an application's execution time is spent executing 10% of the application's code.…”