A compiler infrastructure for embedded heterogeneous MPSoCs

Sheng, Weihua; Schürmans, Stefan; Odendahl, Maximilian; Bertsch, Mark; Volevach, Vitaliy; Leupers, Rainer; Ascheid, Gerd

doi:10.1145/2442992.2442993

Cited by 6 publications

(8 citation statements)

References 19 publications

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“…e major components are discussed in the following. e mapper receives a KPN application wri en in the language "C for process Networks" [38]. In a KPN graph, nodes are computational processes that exchange data only through FIFO channels (the edges of the graph) using atomic data items called tokens.…”

Section: Kpn Mapping Owmentioning

confidence: 99%

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Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design Centering

Hempel

Goens

Castrillón

et al. 2017

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems

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Embedded systems are o en designed as complex architectures with numerous processing elements. E ectively programming such systems requires parallel programming models, e.g. task-based or data ow-based models. With these types of models, the mapping of the abstract application model to the existing hardware architecture plays a decisive role and is usually optimized to achieve an ideal resource footprint or a near-minimal execution time. However, when mapping several independent programs to the same platform, resource con icts can arise. is can be circumvented by remapping some of the tasks of an application, which in turn a ect its timing behavior, possibly leading to constraint violations. In this work we present a novel method to compute mappings that are robust against local task remapping. e underlying method is based on the bio-inspired design centering algorithm of L p-Adaptation. We evaluate this with several benchmarks on di erent platforms and show that mappings obtained with our algorithm are indeed robust. In all experiments, our robust mappings tolerated signi cantly more run-time perturbations without violating constraints than mappings devised with optimization heuristics.

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Section: Kpn Mapping Owmentioning

confidence: 99%

“…In data ow graphs or process networks, the entities cannot communicate over shared memory, which makes these models appropriate for distributed memory architectures. Many languages and models exist to represent such graphs, e.g., Cal [13], YAPI [11], C for process networks [38] or the Distributed Object Layer (DOL) [45].…”

mentioning

confidence: 99%

Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design Centering

Hempel

Goens

Castrillón

et al. 2017

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems

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“…Since a larger load imbalance results in a larger decrease in value of α ef f (as can be concluded from Karp and Flatt (1990), α ef f is a kind of derivative of relative speedup), problems can be identified better than from speedup values. If the parallelization is well-organized (load balanced, small overhead, Sheng et al (2014) right number of processors), α ef f saturates at unity, so tendencies can be better displayed through using (1 − α ef f ).…”

Section: Practical Applicationsmentioning

confidence: 99%

“…In paper Sheng et al (2014) a compiler making effective parallelization of an originally sequential code for different number of cores is described and validated by running the executable code on platforms having the corresponding number of cores. Let us apply Equ.…”

Section: Characterizing Parallelization Effortsmentioning

confidence: 99%

A figure of merit for describing the performance of scaling of parallelization

Végh¹,

Molnár²,

Vásárhelyi³

2016

Preprint

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With the spread of multi-and many-core processors more and more typical task is to re-implement some source code written originally for a single processor to run on more than one cores. Since it is a serious investment, it is important to decide how much efforts pays off, and whether the resulting implementation has as good performability as it could be. The Amdahl's law provides some theoretical upper limits for the performance gain reachable through parallelizing the code, but it needs the detailed architectural knowledge of the program code, does not consider the housekeeping activity needed for parallelization and cannot tell how the actual stage of parallelization implementation performs. The present paper suggests a quantitative measure for that goal. This figure of merit is derived experimentally, from measured running times, and number of threads/cores. It can be used to quantify the used parallelization technology, the connection between the computing units, the acceleration technology under the given conditions, or the performance of the software team/compiler.

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“…It is a challenging task to support OpenCL program model on multicore DSP for embedded application. We address this problem by firstly utilizing the LLVM (low level virtual machine) [5] and Clang [6] open source compiler to support kernel compilation and further optimization for the DSP platform; then we designed 2 Advances in Mechanical Engineering [7,8] scheduler that aimed to schedule work-item in a work group to decrease the task switching overhead. Finally, we proposed a kind of software managed CACHE method to efficiently administrate the distributed global memory which was combined through interconnections such as PCIE, SRIO (serial rapid IO), Hyperlink, and SGMII.…”

Section: Introductionmentioning

confidence: 99%

A Two-Level Task Scheduler on Multiple DSP System for OpenCL

Tian

Cai

Zhou

2014

Advances in Mechanical Engineering

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This paper addresses the problem that multiple DSP system does not support OpenCL programming. With the compiler, runtime, and the kernel scheduler proposed, an OpenCL application becomes portable not only between multiple CPU and GPU, but also between embedded multiple DSP systems. Firstly, the LLVM compiler was imported for source-to-source translation in which the translated source was supported by CCS. Secondly, two-level schedulers were proposed to support efficient OpenCL kernel execution. The DSP/BIOS is used to schedule system level tasks such as interrupts and drivers; however, the synchronization mechanism resulted in heavy overhead during task switching. So we designed an efficient second level scheduler especially for OpenCL kernel work-item scheduling. The context switch process utilizes the 8 functional units and cross path links which was superior to DSP/BIOS in the aspect of task switching. Finally, dynamic loading and software managed CACHE were redesigned for OpenCL running on multiple DSP system. We evaluated the performance using some common OpenCL kernels from NVIDIA, AMD, NAS, and Parboil benchmarks. Experimental results show that the DSP OpenCL can efficiently exploit the computing resource of multiple cores.

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A compiler infrastructure for embedded heterogeneous MPSoCs

Cited by 6 publications

References 19 publications

Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design Centering

Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design Centering

A figure of merit for describing the performance of scaling of parallelization

A Two-Level Task Scheduler on Multiple DSP System for OpenCL

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