A complete high-speed voltage output 16-bit monolithic DAC

Naylor, J.

doi:10.1109/jssc.1983.1052024

Cited by 35 publications

(5 citation statements)

References 5 publications

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“…However, the system becomes sensitive to material stresses and therefore needs to be trimmed after the die has been mounted in its encapsulation. An example of a trimmed high-resolution converter is given in reference [64]. Such procedures are fairly expensive.…”

Section: / a Converter Specificationsmentioning

confidence: 99%

CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters

Plassche¹

2003

254

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Section: / a Converter Specificationsmentioning

confidence: 99%

CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters

Plassche¹

2003

254

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“…Equation 19is the same as (15), which means that the feedback signal in the first-stage output is canceled by the second-stage output C2. This ensures a stable second-stage MASH operation and results in triple-integration noiseshaping characteristics.…”

Section: Improvement Of Stabilitymentioning

confidence: 99%

“…Generally, the output DAC for the noise-shaping D-to-A converter uses a switched-capacitor circuit [11], [12], [15]. For high-accuracy D-to-A conversion, however, it is not suitable because the switched-capacitor circuit suffers accuracy degradation from clock feedthrough noise and settling error noise.…”

Section: A Configuration Oj Differential P Wm Circuitmentioning

confidence: 99%

A 17 bit oversampling D-A conversion technology using multistage noise shaping

Matsuya

Uchimura

Iwata

et al. 1989

IEEE J. Solid-State Circuits

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This paper dkcusses a higbfy stable, triple-integration noiseshaping technique and a precise differential pulse-width modulation (PWM) output method, which permits greater accuracy in monolithic audio D-to-A converters (DAC'S), without trimming. Based on these new techniques, using 1.5-pm CMOS technology, a 17-bit 20-kHz bandwidth DAC LSI with d@d filters was successfully developed. An SNR (S/(N + THD)) of 101 dB and a THD of 0.0007 percent at full-wale input were obtained.

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“…Firstly, the accuracy of the DAC depends on the matching tolerance of the resistors that constitute the ladder; 8~10-bit DACs have been common practice in existing processes with careful layout. For 12-bit resolution or above, some designs choose the segmented R-2R ladder architecture [16], and several studies focusing on improving the linearity have been carried out. The laser trimming technique [17] using thin/thick film process can improve the linearity effectively, but it needs extra manufacturing layers and large area for trimming, which increases the cost.…”

Section: Introductionmentioning

confidence: 99%

“…As for the trimming procedure, the calibration algorithm of the traditional R-2R DAC needs to record the output values, so as to extract the resistance weight of each bit, and then calculate the trimming code. Since trimming one bit of the DAC will affect the weight of other bits, trimming is done for each bit from the LSB to the MSB [16,17]. The procedure needs to trim the resistors for many times, which is complicated and not efficient.…”

Section: Introductionmentioning

confidence: 99%