A Complete Logic BIST Technology with No Storage Requirement

Abstract

Mixed-mode BIST enhances test efficiency of digital circuits by combining the advantages of both pseudorandom and deterministic patterns. In order to apply the deterministic patterns, most traditional methods need to store some test data in external testers or on-chip memory. In this paper we present a novel mixed-mode BIST technique by which all deterministic patterns can be generated on chip in real time and thus requiring no storage device. By appropriately connecting some internal nets of the circuit under test to the inputs of the circuit, together with a set of pseudo-random patterns, this BIST scheme can reach full fault coverage in a very short time. Experimental results show that all irredundant stuck-at faults in each of the ISCAS85 benchmarks can be detected in less than 1000 test cycles with no storage space required.

A new BIST scheme with encoding logic to achieve complete fault coverage

“…The test application time is compared with related BIST solutions without storage memories, as shown in the table, they contains paper [2], paper [9], paper [11] and paper [16]. The last column is the test application time and the hardware cost of ours where the hardware cost is measured by the number of gate they contain.…”

“…Paper [15] illustrates a BIST architecture for fault diagnosis that can be used to identify permanent failures in embedded ROM. A Complete Logic BIST Technology with No Storage Requirement was presented in paper [16]. Though these BIST schemes reduce the size of test set efficiently, and some need not storage memory, the long test application time and the high hardware cost are also the difficulties of the BIST.…”

Efficient LFSR Reseeding Based on Internal-Response Feedback

“…To ensure sufficiently high fault coverage, different sets of connections and corresponding initial stored patterns are thus required, which leads to high area overhead. In [13], a mixed-mode BIST method is proposed, where all deterministic patterns can be generated on chip in real-time, thereby obviating the need for a storage device. By using a set of pseudo-random patterns together with the required deterministic patterns generated by appropriately connecting some internal nets, this BIST scheme can achieve high fault coverage in a very short time.…”

“…By using a set of pseudo-random patterns together with the required deterministic patterns generated by appropriately connecting some internal nets, this BIST scheme can achieve high fault coverage in a very short time. Based on the results in [13], an efficient net identification algorithm is proposed in [12] to identify a minimum set of internal nets for the test architecture in [13]. However, the methods in [12,13] still require many sets of internal nets to generate all deterministic patterns.…”

“…Based on the results in [13], an efficient net identification algorithm is proposed in [12] to identify a minimum set of internal nets for the test architecture in [13]. However, the methods in [12,13] still require many sets of internal nets to generate all deterministic patterns. Also, all the methods in [5,12,13] need to use one multiplexer for each input to select different internal nets.…”