A Complete Single-Chip GPS Receiver With 1.6-V 24-mW Radio in 0.18-&amp;lt;tex&amp;gt;$mu$&amp;lt;/tex&amp;gt;m CMOS

Kadoyama, T.; Suzuki, Norihito; Sasho, N.; Iizuka, H.; Nagase, Ikuho; Usukubo, H.; Katakura, Masayuki

doi:10.1109/jssc.2004.825233

Cited by 61 publications

(5 citation statements)

References 11 publications

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“…Applications relying on GNSS positioning have become a part of everyday life, leading to an increased variety of Location-Based Services (LBS). Nowadays, the LBS consumer market is dominated by single frequency (typically L1/E1 band), low cost and highly integrated GNSS receivers [3][4][5][6][7][8][9]. The use of such receivers comes with two main limitations: low precision and low reliability.…”

Section: Introductionmentioning

confidence: 99%

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Borejko

Marcinek

Siwiec

et al. 2020

Sensors

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A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program.

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Section: Introductionmentioning

confidence: 99%

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Borejko

Marcinek

Siwiec

et al. 2020

Sensors

View full text Add to dashboard Cite

show abstract

“…Location-based services (LBS) utilizing GNSS positioning have become a part of everyday life. Nowadays, the LBS consumer market is dominated by single-frequency GPS (US global positioning system) C/A (coarse acquisition signal) only and low-cost, highly integrated GNSS receivers [3][4][5][6][7][8][9]. However, low precision and low reliability are their main limitations.…”

Section: Introductionmentioning

confidence: 99%

GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing

Marcinek

Pleskacz

2020

Sensors

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This work presents the results of research toward designing an instruction set extension dedicated to Global Navigation Satellite System (GNSS) baseband processing. The paper describes the state-of-the-art techniques of GNSS receiver implementation. Their advantages and disadvantages are discussed. Against this background, a new versatile instruction set extension for GNSS baseband processing is presented. The authors introduce improved mechanisms for instruction set generation focused on multi-channel processing. The analytical approach used by the authors leads to the introduction of a GNSS-instruction set extension (ISE) for GNSS baseband processing. The developed GNSS-ISE is simulated extensively using PC software and field-programmable gate array (FPGA) emulation. Finally, the developed GNSS-ISE is incorporated into the first-in-the-world, according to the authors’ best knowledge, integrated, multi-frequency, and multi-constellation microcontroller with embedded flash memory. Additionally, this microcontroller may serve as an application processor, which is a unique feature. The presented results show the feasibility of implementing the GNSS-ISE into an embedded microprocessor system and its capability of performing baseband processing. The developed GNSS-ISE can be implemented in a wide range of applications including smart IoT (internet of things) devices or remote sensors, fostering the adaptation of multi-frequency and multi-constellation GNSS receivers to the low-cost consumer mass-market.

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“…Radio frequency (RF) and/or analog circuits are now widely integrated with digital baseband processing circuits into a single chip as an RF system on a chip (SoC). [1][2][3][4][5] In the design of RF circuits, however, measurement results are sometimes different from simulation results because of an inaccurate estimation of noise or interference from the surroundings caused by the insufficient accuracy and performance of simulation tools. In particular, analog and RF blocks are sometimes interfered by the nearby digital circuits through the power line and/or the substrate.…”

Section: Introductionmentioning

confidence: 99%

Postfabrication Independent Inductance and Quality Factor Adjustments of On-Chip Inductors by Above-CMOS Processing for Rapid Prototyping of Radio Frequency System on Chips

Sasaki¹,

Kotani

2012

Jpn. J. Appl. Phys.

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The flexible adjustment of on-chip inductor characteristics after a regular complementary metal–oxide–semiconductor (CMOS) fabrication was realized by the “above-CMOS” processing technology for radio frequency (RF) system-on-a-chip (SoC) rapid prototyping. It is shown that the above-CMOS metal pattern formation in a chip-by-chip manner can both increase and decrease the inductance (L) values of on-chip inductors. It is realized by applying various planar patterns of a metal layer deposited on the passivation layer of the chip. To increase the modification range of the characteristics and to establish an independent L and quality factor (Q) adjustment scheme, we have newly developed a pre-design method and a Q-compensation method. By combining these methods, the effective L and Q values of the on-chip inductors can be independently and arbitrarily modified. The adjustment of the input impedance matching frequency of a low-noise amplifier (LNA) using this scheme has also been demonstrated.

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A Complete Single-Chip GPS Receiver With 1.6-V 24-mW Radio in 0.18-<tex>$mu$</tex>m CMOS

Cited by 61 publications

References 11 publications

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing

Postfabrication Independent Inductance and Quality Factor Adjustments of On-Chip Inductors by Above-CMOS Processing for Rapid Prototyping of Radio Frequency System on Chips

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