A complete solution for the power delivery system (PDS) design for high-speed digital systems

Nabil, Shaymaa M.; El-Rouby, Alaa; Hussin, Ahmad

doi:10.1109/dtis.2009.4938051

Cited by 5 publications

(4 citation statements)

References 6 publications

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“…In [5], the authors show that in the PSO algorithm, there would be a better result if p 2 is less than "1" and p 1 is between [4,10], and p 1 should decrease and p 2 should increase as the number of iteration increases. Therefore, we would set parameter p 1max , p 1min , p 2max and p 2min to define the boundaries of p 1 and p 2 .…”

Section: Pdc-psomentioning

confidence: 99%

Cost-effective decap selection for beyond die power integrity

Chen¹,

Tsai²,

Chen³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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1 Abstract-In designing reliable power distribution networks (PDN) for power integrity (PI), it is essential to stabilize voltage supply to devices on chip. We usually employ decoupling capacitor (decap) to suppress the noise generated by the switching of devices. There have been numerous prior works on how to select/insert decaps in chip, package, or board to maintain PI, however optimal decap selection is usually not applicable due to design budget and manufacturability. Moreover, design cost is seldom touched or mentioned. In this research, we propose an efficient methodology "PDC-PSO" to automatically optimizing the selection of available decaps. This algorithm not only takes advantage of particle swarm optimization (PSO) to stochastically search the design space, but takes the most effective range of decaps into consideration to outperform the basic PSO. We apply this to three real package designs and the results show that, compared to the original decap selection by rules of thumb, our approach could shorten the design period and we have better combination of decaps at the same or lower cost. In addition, our methodology can also consider package-board co-design in optimizing different operation frequencies.

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Section: Pdc-psomentioning

confidence: 99%

Cost-effective decap selection for beyond die power integrity

Chen¹,

Tsai²,

Chen³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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“…Each solution has its limitations regarding the board stack‐up, the range of frequencies, the parasitics inclusion, and the circuit application. For example Simple calculation based on the charge sharing 2 neither counts for the capacitor impedance nor for the system impedance. In 3 they tried to model the board resistance and inductance as lumped elements, which is not proper for high‐speed boards. The capacitor ratio approach 2 assumed ideal capacitors without taking the capacitor or the board routing inductance into consideration; hence, it results in a non‐accurate solution. In 4 they took the inductance of the capacitors into account but ignored the inductance of the board. Another interesting method is the extended adaptive voltage positioning (EAVP) 5, where they considered the capacitor's placement through the utilization of a 3D field solver, similar to our approach. Two other reliable methods were presented in 6, 7 where the board and the capacitors parasitic are taken into consideration.However, these methods 5–7 assume that the impedance of the power distribution network (PDN) should be kept below some fixed impedance value called the target impedance, which resulted in over designed boards. This assumption is not accurate as will be explained in Section 3.2.…”

Section: Introductionmentioning

confidence: 99%

“…Two other reliable methods were presented in 6, 7 where the board and the capacitors parasitic are taken into consideration.…”

Section: Introductionmentioning

confidence: 99%

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An accurate power delivery system (PDS) design methodology for high‐speed digital systems

Nabil

El-Rouby

Khalil

2010

Circuit Theory & Apps

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SUMMARYThe trend in high-speed digital circuits is to increase speed and density and to operate at lower voltage. This fast increase in the switching speed combined with the decrease of the operating voltage causes the allowable absolute voltage variations to decrease, which makes the PDS design a more challenging task than ever.Moreover, the complex 3D nature of the modern PDS causes it to be more sensitive to capacitors' placement as well as capacitance value.In this paper, we introduce an efficient complete solution for the design of high-speed digital PDS. This solution (a) takes the effects of the decoupling capacitor placement into consideration through a 3D electromagnetic simulation of the PDS, (b) defines a more-realistic PDS design target, and (c) presents a clear capacitor value selection methodology. Finally, we applied our methodology to an industrial test case, compared its results with that of industrial design, and showed its advantages.

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